ARM DS-5 Manual page 35

Signal I/O
DBGRQ Output
DBGACK Input
SWDIO (SWD Input/
mode) Output
SWCLK(SWD Output
mode)
SWO (SWD mode) Input
VTREF Input
GND -
ARM 100956_0527_00_en
Description
The Debug Request pin stops the target processor and puts it into debug state. DBGRQ is rarely
used by current systems and is usually pulled LOW on the target.
The Debug Acknowledge pin notifies DSTREAM that a debug request has been received and the
target processor is now in debug state. DBGACK is rarely used by current systems and is usually
pulled LOW on the target.
The Serial Wire Data I/O pin sends and receives serial data to and from the target during
debugging. You are advised to series terminate SWDIO close to the target processor.
The Serial Wire Clock pin clocks data into and out of the target during debugging.
The Serial Wire Output pin provides trace data to DSTREAM. You are advised to series terminate
SWO close to the target processor.
The Voltage Target Reference pin supplies DSTREAM with the debug rail voltage of the target to
match its I/O logic levels. VTREF can be tied HIGH on the target. If VTREF is pulled HIGH by
a resistor, its value must be no greater than 100Ω.
Ground.
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2 ARM DSTREAM Target Interface Connections
2.4 The ARM JTAG 20 connector pinouts and interface signals
Table 2-7 ARM JTAG 20 signals (continued)
2-35