Table 2-7 Arm Jtag 20 Signals - ARM DS-5 Manual

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2.4.3
ARM JTAG 20 interface signals
The table describes the signals on the ARM JTAG 20 interface.
Signal
I/O
TDI
Output
TDO
Input
TMS
Output
TCK
Output
RTCK
Input
nTRST
Output
nSRST
Input/
Output
ARM 100956_0527_00_en
Description
The Test Data In pin provides serial data to the target during debugging. TDI can be pulled HIGH
on the target.
The Test Data Out pin receives serial data from the target during debugging. You are advised to
series terminate TDO close to the target processor. TDO is typically pulled HIGH on the target.
The Test Mode Select pin sets the state of the Test Access Port (TAP) controller on the target.
TMS can be pulled HIGH on the target to keep the TAP controller inactive when not in use.
The Test Clock pin clocks data into the TDI and TMS inputs of the target. TCK is typically
pulled HIGH on the target.
The Return Test Clock pin echos the test clock signal back to DSTREAM for use with adaptive
mode clocking. If RTCK is generated by the target processor, you are advised to series terminate
it. RTCK can be pulled HIGH or LOW on the target when not in use.
The Test Reset pin resets the TAP controller of the processor to allow debugging to take place.
nTRST is typically pulled HIGH on the target and pulled strong-LOW by DSTREAM to initiate a
reset. The polarity and strength of nTRST is configurable.
The System Reset pin fully resets the target. This signal can be initiated by DSTREAM or by the
target board (which is then detected by DSTREAM). nSRST is typically pulled HIGH on the
target and pulled strong-LOW to initiate a reset. The polarity and strength of nSRST is
configurable.
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2 ARM DSTREAM Target Interface Connections
2.4 The ARM JTAG 20 connector pinouts and interface signals
Table 2-6 ARM JTAG 20 interface pinout table (continued)
Pin Signal name I/O diagram Voltage domain
6
GND
7
TMS/SWDIO B/C
8
GND
9
TCK/SWCLK B
10
GND
11
RTCK
12
GND
13
TDO/SWO
14
GND
15
nSRST
16
GND
17
DBGRQ
18
GND
19
DBGACK
20
GND
H
NA
A
H
NA
A
H
NA
A
A
H
NA
A
A
H
NA
E
A
H
NA
B
A
H
NA
A
A
H
NA

Table 2-7 ARM JTAG 20 signals

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