Figure 1-4 Timing Diagram For The D-Type Jtag Synchronizer - ARM DS-5 Manual

1 ARM DSTREAM System Design Guidelines
1.1 About adaptive clocking to synchronize the JTAG port
The following figure shows a corresponding partial timing diagram, and how TCKFallingEn and
TCKRisingEn are each active for exactly one period of CLK. It also shows how these enable signals
gate the RTCK and TDO signals so that they only change state at the edges of TCK.
TCK
CLK
TCKRisingEn
TCKFallingEn
RTCK
TAPC
State
TDO

Figure 1-4 Timing diagram for the D-type JTAG synchronizer

Related references
1.2 Reset signals on page 1-16.
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