ARM DS-5 Manual page 44

Signal I/O
nTRST Output
nSRST Input/
Output
DBGRQ Output
DBGACK Input
SWDIO (SWD Input/
mode) Output
SWCLK(SWD Output
mode)
SWO (SWD mode) Input
TraceD[0-3] Input
TRACECLK (Trace Input
mode)
VTREF Input
GND -
KEY -
ARM 100956_0527_00_en
Description
The Test Reset pin resets the TAP controller of the processor to allow debugging to take place.
nTRST is typically pulled HIGH on the target and pulled strong-LOW by DSTREAM to initiate a
reset. The polarity and strength of nTRST is configurable.
The System Reset pin fully resets the target. This signal can be initiated by DSTREAM or by the
target board (which is then detected by DSTREAM). nSRST is typically pulled HIGH on the
target and pulled strong-LOW to initiate a reset. The polarity and strength of nSRST is
configurable.
The Debug Request pin stops the target processor and puts it into debug state. DBGRQ is rarely
used by current systems and is usually pulled LOW on the target.
The Debug Acknowledge pin notifies DSTREAM that a debug request has been received and the
target processor is now in debug state. DBGACK is rarely used by current systems and is usually
pulled LOW on the target.
The Serial Wire Data I/O pin sends and receives serial data to and from the target during
debugging. You are advised to series terminate SWDIO close to the target processor.
The Serial Wire Clock pin clocks data into and out of the target during debugging.
The Serial Wire Output pin provides trace data to DSTREAM. You are advised to series terminate
SWO close to the target processor. SWO is configurable to be captured on pin 6 or 14.
The Trace Data [0-3] pins provide DSTREAM with TPIU continuous mode trace data from the
target. You are advised to series terminate these signals close to the target processor.
The Trace Clock pin provides DSTREAM with the clock signal necessary to sample the trace data
signals. You are advised to series terminate TRACECLK close to the target processor.
The Voltage Target Reference pin supplies DSTREAM with the debug rail voltage of the target to
match its I/O logic levels. VTREF can be tied HIGH on the target. If VTREF is pulled HIGH by
a resistor, its value must be no greater than 100Ω.
Ground.
This pin must not be present on the target connector.
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2 ARM DSTREAM Target Interface Connections
2.8 The CoreSight 20 connector pinouts and interface signals
Table 2-15 CoreSight 20 signals (continued)
2-44