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2.6.3
ARM JTAG 14 interface signals
The table describes the signals on the ARM JTAG 14 interface.
Signal
I/O
TDI
Output
TDO
Input
TMS
Output
TCK
Output
nTRST
Output
nSRST
Input/
Output
SWDIO (SWD
Input/
mode)
Output
SWCLK(SWD
Output
mode)
SWO (SWD mode)
Input
VTREF
Input
GND
-
ARM 100956_0527_00_en
Description
The Test Data In pin provides serial data to the target during debugging. TDI can be pulled
HIGH on the target.
The Test Data Out pin receives serial data from the target during debugging. You are advised to
series terminate TDO close to the target processor. TDO is typically pulled HIGH on the target.
The Test Mode Select pin sets the state of the Test Access Port (TAP) controller on the target.
TMS can be pulled HIGH on the target to keep the TAP controller inactive when not in use.
The Test Clock pin clocks data into the TDI and TMS inputs of the target. TCK is typically
pulled HIGH on the target.
The Test Reset pin resets the TAP controller of the processor to allow debugging to take place.
nTRST is typically pulled HIGH on the target and pulled strong-LOW by DSTREAM to initiate
a reset. The polarity and strength of nTRST is configurable.
The System Reset pin fully resets the target. This signal can be initiated by DSTREAM or by the
target board (which is then detected by DSTREAM). nSRST is typically pulled HIGH on the
target and pulled strong-LOW to initiate a reset. The polarity and strength of nSRST is
configurable.
The Serial Wire Data I/O pin sends and receives serial data to and from the target during
debugging. You are advised to series terminate SWDIO close to the target processor.
The Serial Wire Clock pin clocks data into and out of the target during debugging.
The Serial Wire Output pin provides trace data to DSTREAM. You are advised to series
terminate SWO close to the target processor.
The Voltage Target Reference pin supplies DSTREAM with the debug rail voltage of the target to
match its I/O logic levels. VTREF can be tied HIGH on the target. If VTREF is pulled HIGH by
a resistor, its value must be no greater than 100Ω.
Ground.
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2 ARM DSTREAM Target Interface Connections
2.6 The ARM JTAG 14 connector pinouts and interface signals
Table 2-10 ARM JTAG 14 interface pinout table (continued)
Pin Signal name I/O diagram Voltage domain
8
GND
9
TCK/SWCLK B
10
GND
11
TDO/SWO
12
nSRST
13
VTREF
14
GND
H
NA
A
H
NA
A
A
E
A
F
A
H
NA
Table 2-11 ARM JTAG 14 signals
2-39
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