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2.8
The CoreSight 20 connector pinouts and interface signals
This describes the CoreSight 20 connector.
This section contains the following subsections:
•
2.8.1 About the CoreSight 20 connector on page
•
2.8.2 CoreSight 20 pinouts on page
•
2.8.3 CoreSight 20 interface signals on page
2.8.1
About the CoreSight 20 connector
You can use the CoreSight 20 connector in either standard JTAG (IEEE 1149.1) mode or Serial Wire
Debug (SWD) mode. It can also optionally capture up to 4 bits of parallel trace in Trace Port Interface
Unit (TPIU) continuous mode.
When this connector is configured to be a parallel trace source, pins 12 to 20 switch to their alternate
trace functions.
The following figure shows the CoreSight 20 connector pinout:
A polarizing key is fitted only at the target end of the cable.
Related concepts
2.12 Series termination on page 2-52.
Related references
2.2 Target connectors supported by DSTREAM on page 2-28.
2.10 I/O diagrams for the DSTREAM probe connectors on page 2-49.
2.11 Voltage domains of the DSTREAM probe on page 2-51.
2.8.2 CoreSight 20 pinouts on page 2-42.
2.8.3 CoreSight 20 interface signals on page 2-43.
Related information
ETMv1 and ETMv3 architecture pinouts.
2.8.2
CoreSight 20 pinouts
The table shows the CoreSight 20 pinouts as used on the target board.
ARM 100956_0527_00_en
Note
Copyright © 2010–2012, 2015–2017 ARM Limited or its affiliates. All rights reserved.
2 ARM DSTREAM Target Interface Connections
2.8 The CoreSight 20 connector pinouts and interface signals
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2-43.
Figure 2-10 CoreSight 20 connector pinout
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