Figure 1-7 Timing Diagram For The D-Type Jtag Synchronizer - ARM DSTREAM-PT Reference Manual

1 Debug and trace interface
1.1 JTAG signals
The following figure shows a corresponding partial timing diagram, and how TCKFallingEn and
TCKRisingEn are each active for exactly one period of CLK. It also shows how these enable signals
gate the RTCK and TDO signals so that they only change state at the edges of TCK.
TCK
CLK
TCKRisingEn
TCKFallingEn
RTCK
TAPC
State
TDO

Figure 1-7 Timing diagram for the D-type JTAG synchronizer

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