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R/W
ACKE
R
ACKD
R/W
BSYE
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Note
The busy mode can be cleared by start of serial interface transfer. However, the BSYE flag is not cleared
to 0.
Remark CSIE0: Bit 7 of the serial operating mode register 0 (CSIM0)
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries)
Acknowledge Signal Automatic Output Control (in the SBI mode)
0
Acknowledge signal automatic output disable (output with ACKT enable)
1
Before completion
of transfer
After completion
of transfer
Acknowledge Detection
Clear Conditions (ACKD = 0)
• In the SBI mode, at the falling edge of SCK0 clock
immediately after the busy mode has been released
when a transfer start instruction is executed
• When CSIE0 = 0
• When RESET input is applied
Synchronizing Busy Signal Output Control
Note
0
When the SBI mode is used, disables busy signal which is output in synchronization with the falling edge of
SCK0 clock immediately after execution of the instruction to be cleared to 0 (with READY state).
1
When the SBI mode is used, outputs busy signal at the falling edge of SCK0 clock following the
acknowledge signal.
Acknowledge signal is output in synchronization with the 9th clock
falling edge of SCK0 (automatically output when ACKE = 1).
Acknowledge signal is output in synchronization with the falling edge of SCK0
clock immediately after execution of the instruction to be set to 1 (automatically
output when ACKE = 1). However, not automatically cleared to 0 after acknowl
edge signal output.
Set Conditions (ACKD = 1)
• When acknowledge signal (ACK) is detected at the
rising edge of SCK0 clock after completion of transfer
(continued)
355
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