NEC 78014Y Series User Manual page 274

R COI
0
1
R/W CSIE0
0
1
Note When CSIE0 = 0, COI becomes 0.
(3) Serial bus interface control register (SBIC)
This register sets serial bus interface operation and displays status.
SBIC is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets SBIC to 00H.
Symbol <7>
SBIC BSYE ACKD ACKE
R/W RELT
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R/W CMDT
R RELD
Clear Conditions (RELD = 0)
• When transfer start instruction is executed
• If SIO0 and SVA values do not match in address
reception
• When CSIE0 = 0
• When RESET input is applied
Note Bits 2, 3 and 6 (RELD, CMDD and ACKD) are Read-Only bits.
Remark CSIE0: Bit 7 of the serial operating mode register 0 (CSIM0)
274
CHAPTER 15 SERIAL INTERFACE CHANNEL 0 ( µ PD78014 Subseries)
Figure 15-5. Serial Operating Mode Register 0 Format (2/2)
Slave Address Comparison Result Flag
Slave address register (SVA) not equal to serial I/O shift register 0 (SIO0) data
Slave address register (SVA) equal to serial I/O shift register 0 (SIO0) data
Serial Interface Channel 0 Operation Control
Operation stopped
Operation enabled
Figure 15-6. Serial Bus Interface Control Register Format (1/2)
<6> <5> <4> <3>
ACKT CMDD RELD CMDT
Use for bus release signal output.
When RELT = 1, SO latch is set to 1. After SO latch setting, automatically cleared to 0.
Also cleared to 0 when CSIE0 = 0.
Use for command signal output.
When CMDT = 1, SO latch is cleared to (0). After SO latch clearance, automatically cleared to (0).
Also cleared to (0) when CSIE0 = 0.
Bus Release Detection
Note
<2> <1> <0> Address
RELT FF61H
Set Conditions (RELD = 1)
• When bus release signal (REL) is detected
When Reset R/W
00H R/W Note