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CHAPTER 5 CPU ARCHITECTURE
Figure 5-11. General Register Configuration
BANK0
BANK1
BANK2
BANK3
BANK0
BANK1
BANK2
BANK3
(a) Absolute Name
16-Bit Processing
RP3
RP2
RP1
RP0
15
0
(b) Function Name
16-Bit Processing
HL
DE
BC
AX
15
0
8-Bit Processing
R7
R6
R5
R4
R3
R2
R1
R0
7
0
8-Bit Processing
H
L
D
E
B
C
A
X
7
0
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