NEC 78014Y Series User Manual page 513

Instruc- Mnemonic
tion
Group
Call
Return
Stack
Manipu-
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lation
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
Operands
CALL !addr16
CALLF !addr11
CALLT [addr5]
BRK
RET
RETI
RETB
PUSH PSW
rp
POP PSW
rp
MOVW SP, #word
SP, AX
AX, SP
register (PCC).
2. Clock indicates when a program is in the internal ROM area.
CHAPTER 23 INSTRUCTION SET
Byte Clock
Note 1 Note 2
3 14 —
2 10 —
1 12 —
1 12 —
1 12 —
1 12 —
1 12 —
1 4 —
1 8 —
1 4 —
1 8 —
4 — 20
2 — 16
2 — 16
Operation
(SP–1) ← (PC+3) , (SP–2) ← (PC+3)
H
PC ← addr16, SP ← SP–2
(SP–1) ← (PC+2) , (SP–2) ← (PC+2)
H
← 00001, PC ← addr11,
PC
15–11 10–0
SP ← SP–2
(SP–1) ← (PC+1) , (SP–2) ← (PC+1)
H
← (00000000, addr5+1),
PC
H
← (00000000, addr5),
PC
L
SP ← SP–2
(SP–1) ← PSW, (SP–2) ← (PC+1)
(SP–3) ← (PC+1) ← (003FH),
, PC
L H
← (003EH), SP ← SP–3, IE ← 0
PC
L
← (SP+1), PC ← (SP),
PC
H L
SP ← SP+2
← (SP+1), PC ← (SP),
PC
H L
PSW ← (SP+2), SP ← SP+3,
NMIS ← 0
← (SP+1), PC ← (SP),
PC
H L
PSW ← (SP+2), SP ← SP+3
(SP–1) ← PSW, SP ← SP–1
(SP–1) ← rp , (SP–2) ← rp
,
H L
SP ← SP–2
PSW ← (SP), SP ← SP+1
← (SP+1), rp ← (SP),
rp
H L
SP ← SP+2
SP ← word
SP ← AX
AX ← SP
) selected by processor clock control
CPU
Flag
Z AC CY
,
L
,
L
,
L
,
H
R R R
R R R
R R R
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