NEC 78014Y Series User Manual page 329

8-bit single-chip microcontrollers
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Serial Transfer Mode
3-wire or 2-wire serial I/O mode
SBI mode
I
2
C bus mode (transmit)
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I
2
C bus mode (receive)
Remark ACKE: Bit 5 of serial bus interface control register (SBIC)
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries)
Table 16-4. Serial Interface Channel 0 Interrupt Request Signal Generation
WUP
0
Other than above
0
1
Other than above
0
Other than above
0
1
Other than above
WAT1 WAT0 ACKE
0
0
0
An interrupt request signal is generated each time 8 serial
clocks are counted.
Setting prohibited
0
0
0/1
An interrupt request signal is generated each time 8 serial
clocks are counted (8-clock wait).
After address is received, if the values of the serial I/O shift
register 0 (SIO0) and the slave address register (SVA)
match, an interrupt request signal is generated.
Setting prohibited
1
0
0
An interrupt request signal is generated each time 8 serial
clocks are counted (8-clock wait).
Normally, during transmission the settings WAT1, WAT0
= 1, 0, are not used. They are used only when wanting
to coordinate receive time and processing systematically
using software. ACK information is generated by the
receiving side, thus ACKE should be set to 0 (disable).
1
1
0
An interrupt request signal is generated each time 9 serial
clocks are counted (9-clock wait).
ACK information is generated by the receiving side, thus
ACKE should be set to 0 (disable).
Setting prohibited
1
0
0
An interrupt request signal is generated each time 8 serial
clocks are counted (8-clock wait). ACK information is
output by manipulating ACKT by software after an interrupt
is generated.
1
1
0/1
An interrupt request signal is generated each time 9 serial
clocks are counted (9-clock wait). To automati
cally generate ACK information, preset ACKE to 1 (enable)
before transfer start. However, in the case of the master,
set ACKE to 0 (disable) before receiving the last data.
1
1
1
After address is received, if the values of the serial I/O shift
register 0 (SIO0) and the slave address register (SVA)
match, an interrupt request signal is generated.
To automatically generate ACK information, preset ACKE
to 1 (enable) before transfer start.
Setting prohibited
Description
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