NEC 78014Y Series User Manual page 335

R/W ACKE
R/W ACKE
R ACKD
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R/W
BSYE
Notes
Remark CSIE0: Bit 7 of the serial operating mode register 0 (CSIM0)
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries)
Figure 16-7. Serial Bus Interface Control Register Format (2/2)
Acknowledge Signal Automatic Output Control (in SBI mode)
0 Acknowledge signal automatic output disable (output with ACKT enable)
1 Before completion
of transfer
After completion
of transfer
Acknowledge Signal Automatic Output Control
0 Disables acknowledge signal automatic output. (However, output with ACKT possible)
Use for reception when 8-clock wait mode is selected or for transmission
1 Enables acknowledge signal automatic output.
Outputs acknowledge signal in synchronization with the 9th clock falling edge of SCL (automatically output
when ACKE = 1). However, not automatically cleared to 0 after acknowledge signal output.
Used in reception with 9-clock wait mode selected.
Acknowledge Detection
Clear Conditions (ACKD = 0)
• At the falling edge of SCK0 clock immediately after the
busy mode has been released when a transfer start
instruction is executed
• Upon execution of transfer start instruction in the I
bus mode
• When CSIE0 = 0
• When RESET input is applied
Note 3 Synchronizing Busy Signal Output Control
0 When the SBI mode is used, disables busy signal which is output in synchronization with the falling edge of
SCK0 clock immediately after
to 0 in the I 2 C bus mode.
1 Outputs busy signal at the falling edge of SCK0 clock following the acknowledge signal when the SBI mode
is used.
1. Setting should be performed before transfer.
2. If 8-clock wait mode is selected, the acknowledge signal at reception time must be output using ACKT.
3. The busy mode can be cancelled by start of serial interface.
However, the BSYE flag is not cleared to 0.
Acknowledge signal is output in synchronization with the 9th clock falling edge of
SCK0 (automatically output when ACKE = 1).
Acknowledge signal is output in synchronization with the falling edge of SCK0 clock
immediately after execution of the instruction to be set to 1 (automatically output when
ACKE = 1). However, not automatically cleared to 0 after acknowledge signal output.
Note 1
(in the I
Set Conditions (ACKD = 1)
• When acknowledge signal is detected at the rising
2 C
execution of the instruction to be cleared to 0. Be sure to set BSYE
2
C bus mode)
Note 2
.
edge of SCK0/SCL clock after completion of transfer
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