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1.7 Block Diagram
TI0/INTP0/P00
SI0/SB0/P25
SO0/SB1/P26
SCK0/P27
SCK1/P22
BUSY/P24
ANI0/P10 to
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INTP0/P00 to
INTP3/P03
Remarks 1. The internal ROM and RAM capacities depend on the product.
CHAPTER 1 OUTLINE ( µ PD78014 Subseries)
TO0/P30
16-bit TIMER/
EVENT COUNTER
TO1/P31
8-bit TIMER/
EVENT COUNTER 1
TI1/P33
TO2/P32
8-bit TIMER/
EVENT COUNTER 2
TI2/P34
WATCHDOG
TIMER
WATCH TIMER
SERIAL
INTERFACE 0
SI1/P20
SO1/P21
SERIAL
INTERFACE 1
STB/P23
ANI7/P17
AV
A/D
DD
CONVERTER
AV
SS
AV
REF
INTERRUPT
CONTROL
BUZZER OUTPUT
BUZ/P36
CLOCK OUTPUT
PCL/P35
CONTROL
2. Pin connection in parentheses is intended for the µ PD78P014.
78K/0
ROM
CPU CORE
RAM
V
V
IC
DD
SS
(V
)
pp
P00
PORT0
P01 to P03
P04
PORT1
P10 to P17
PORT2
P20 to P27
PORT3
P30 to P37
PORT4
P40 to P47
PORT5
P50 to P57
PORT6
P60 to P67
AD0/P40 to
AD7/P47
A8/P50 to
A15/P57
EXTERNAL
ACCESS
RD/P64
WR/P65
WAIT/P66
ASTB/P67
RESET
X1
SYSTEM
X2
CONTROL
XT1/P04
XT2
45
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