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(4) Capture register data retention timings
If the valid edge of the TI0/P00 pin is input during 16-bit capture register (CR01) read, CR01 holds data without
carrying out capture operation. However, the interrupt request flag (PIF0) is set upon detection of the valid edge.
TM0 Count Value
Interrupt Request Flag
Capture Read Signal
CR01 Captured Value
(5) Valid edge set
Set the valid edge of the TI0/INTP0/P00 pin after setting bits 1 to 3 (TMC01 to TMC03) of the 16-bit timer mode
control register (TMC0) to 0, 0 and 0, respectively, and then stopping timer operation. Valid edge setting is carried
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out with bits 2 and 3 (ES10 and ES11) of the external interrupt mode register (INTM0).
CHAPTER 8 16-BIT TIMER/EVENT COUNTER
Figure 8-22. Capture Register Data Retention Timings
Count Pulse
N
Edge Input
X
N + 1
N + 2
M
M + 1
M + 2
N + 1
Capture Operation
Ignored
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