NEC 78014Y Series User Manual page 275

R CMDD
R/W ACKT
R/W ACKE
R ACKD
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R/W BSYE
Note Busy mode can be cleared by start of serial interface transfer. However, BSYE flag is not cleared to 0.
Remarks 1. Zeros will be returned from bits 0, 1, and 4 (or RELT, CMDT, ACKT, respectively) if users read these
CHAPTER 15 SERIAL INTERFACE CHANNEL 0 ( µ PD78014 Subseries)
Figure 15-6. Serial Bus Interface Control Register Format (2/2)
Command Detection
Clear Conditions (CMDD = 0)
• When transfer start instruction is executed
• When bus release signal (REL) is detected
• When CSIE0 = 0
• When RESET input is applied
Acknowledge signal is output in synchronization with the falling edge of SCK0 clock immediately after
execution of the instruction to be set to 1, and after acknowledge signal output, automatically cleared to 0.
Also cleared to 0 upon start of serial interface transfer or when CSIE0 = 0
Acknowledge Signal Output Control
0 Acknowledge signal automatic output disable (output with ACKT enable)
1 Before completion
of transfer
After completion
of transfer
Acknowledge Detection
Clear Conditions (ACKD = 0)
• At the falling edge of SCK0 immediately after the
busy mode has been released when a transfer start
instruction is executed
• When CSIE0 = 0
• When RESET input is applied
Note Synchronizing Busy Signal Output Control
0 Disables busy signal which is output in synchronization with the falling edge of SCK0 clock immediately
after execution of the instruction to be cleared to 0.
1 Outputs busy signal at the falling edge of SCK0 clock following the acknowledge signal.
bits after data setting is completed.
2. CSIE0: Bit 7 of the serial operating mode register 0 (CSIM0)
Set Conditions (CMDD = 1)
• When command signal (CMD) is detected
Acknowledge signal is output in synchronization with the 9th clock falling edge of
SCK0 (automatically output when ACKE = 1).
Acknowledge signal is output in synchronization with the falling edge of SCK0 clock
immediately after execution of the instruction to be set to 1 (automatically output when
ACKE = 1). However, not automatically cleared to 0 after acknowledge signal output.
Set Conditions (ACKD = 1)
• When acknowledge signal (ACK) is detected at the
rising edge of SCK0 clock after completion of transfer
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