NEC 78014Y Series User Manual page 293

(b) Serial bus interface control register (SBIC)
Symbol
SBIC BSYE ACKD ACKE
R/W
R/W CMDT
R RELD
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R CMDD
R/W ACKT
Note Bits 2, 3, and 6 (RELD, CMDD and ACKD) are Read-Only bits.
Remarks 1. Zeros will be returned from bits 0, 1, and 4 (or RELT, CMDT, ACKT, respectively) if users read these
CHAPTER 15 SERIAL INTERFACE CHANNEL 0 ( µ PD78014 Subseries)
SBIC is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets SBIC to 00H.
<7> <6> <5> <4>
ACKT CMDD RELD CMDT
RELT Use for bus release signal output.
When RELT = 1, SO latch is set to 1. After SO latch setting, automatically cleared to 0.
Also cleared to 0 when CSIE0 = 0.
Use for command signal output.
When CMDT = 1, SO latch is cleared to (0). After SO latch clearance, automatically cleared to (0).
Also cleared to (0) when CSIE0 = 0.
Bus Release Detection
Clear Conditions (RELD = 0)
• When transfer start instruction is executed
• If SIO0 and SVA values do not match in address
reception (only if WUP = 1)
• When CSIE0 = 0
• When RESET input is applied
Command Detection
Clear Conditions (CMDD = 0)
• When transfer start instruction is executed
• When bus release signal (REL) is detected
• When CSIE0 = 0
• When RESET input is applied
Acknowledge signal is output in synchronization with the falling edge clock of SCK0 just after execution of
the instruction to be set to 1, and after acknowledge signal output, automatically cleared to 0. Used as ACKE = 0
Also cleared to 0 upon start of serial interface transfer or when CSIE0 = 0.
bits after data setting is completed.
2. CSIE0: Bit 7 of the serial operating mode register 0 (CSIM0)
<3> <2> <1> <0>
RELT
Set Conditions (RELD = 1)
• When bus release signal (REL) is detected
Set Conditions (CMDD = 1)
• When command signal (CMD) is detected
Address When Reset R/W
FF61H 00H R/W
Note
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