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Symbol
ADTC
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Notes
Caution When an external clock input is selected with bit 1 (CSIM11) of serial operating mode register 1
Remark ×: don't care
CHAPTER 17 SERIAL INTERFACE CHANNEL 1
Figure 17-4. Automatic Data Transmit/Receive Control Register Format
<7>
<6>
<5>
<4>
RE
ARLD ERCE
ERR
1. Bits 3 and 4 (TRF and ERR) are read-only bits.
2. The termination of automatic transmission/reception should be judged by using TRF, not CSIIF1 (interrupt
request flag).
(CSIM1) set to 0, set STRB and BUSY1 of ADTC to 0, 0.
<3>
<2>
<1>
<0>
TRF
STRB BUSY1 BUSY0
R/W
R/W
R
R
R/W
R/W
R/W
Address
When Reset
R/W
FF69H
00H
R/W
BUSY1 BUSY0 Busy Input Control
×
0
Not using busy input
1
0
Busy input enable (active high)
1
1
Busy input enable (active low)
STRB
Strobe Output Control
0
Strobe output disable
1
Strobe output enable
TRF
Status of Automatic Transmit/Receive Function
0
Detection of termination of automatic
transmission/reception (This bit is set to 0
upon suspension of automatic transmission/
reception or when ARLD = 0)
1
During automatic transmission/reception
(This bit is set to 1 when data is written to SIO1)
ERR
Error Detection of Automatic Transmit/
Receive Function
0
No error in automatic transmission/reception
(This bit is set to 0 when data is written to SIO1)
1
Error occurred in automatic transmission/
reception
ERCE
Error Check Control of Automatic Transmit/
Receive Function
0
Error check disable in automatic
transmission/reception
1
Error check enable (only when BUSY1 = 1)
ARLD
Operating Mode Selection of Automatic
Transmit/Receive Function
0
Single operating mode
1
Repetitive operating mode
RE
Receive Control of Automatic Transmit/
Receive Function
0
Receive disable
1
Receive enable
Note 1
Note 2
417
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