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(3) Stack pointer (SP)
This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM
area can be set as the stack area. Internal high-speed RAM of each product is as follows.
µ PD78011B, 78011BY, 78012B, 78012BY: FD00H to FEFFH
µ PD78013, 78013Y, 78014, 78014Y, 78P014, 78P014Y: FB00H to FEFFH
SP
SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8
The SP is decremented ahead of write (save) to the stack memory and is incremented after read (reset) from
the stack memory.
Each stack operation saves/resets data as shown in Figures 5-9 and 5-10.
Caution
Since SP contents will be undefined by RESET input, be sure to initialize the SP before instruction
execution.
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CHAPTER 5 CPU ARCHITECTURE
Figure 5-8. Stack Pointer Configuration
15
SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
0
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