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Signal Name
Output
Definition
Device
Bus release
Master
SB0 (SB1) rising edge
signal (REL)
when SCK0 = 1
Command signal
Master
SB0 (SB1) falling edge
(CMD)
when SCK0 = 1
Acknowledge
Master/
Low-level signal to be
signal (ACK)
slave
output to SB0 (SB1)
during one-clock period
of SCK0 after completion
of serial reception
Busy signal
Slave
[Synchronous BUSY signal]
(BUSY)
Low-level signal to be
output to SB0 (SB1)
following Acknowledge
signal
Ready signal
Slave
High-level signal to be
(READY)
output to SB0 (SB1)
before serial transfer
start and after completion
of serial transfer
Table 15-4. Various Signals in SBI Mode (1/2)
Timing Chart
SCK0
"H"
SB0 (SB1)
SCK0
"H"
SB0 (SB1)
[Synchronous BUSY output]
9
SCK0
ACK
BUSY
SB0 (SB1)
D0
ACK
BUSY
SB0 (SB1)
D0
Output Condition
Effects on Flag
• RELT set
• RELD set
• CMDD clear
• CMDT set
• CMDD set
<1> ACKE = 1
• ACKD set
<2> ACKT set
• BSYE = 1
—
READY
<1> BSYE = 0
—
<2> Execution
READY
of instruction
data write
SIO0 (trans
start
instruction)
Meaning of Signal
CMD signal is output to
indicate that transmit
data is an address.
i) Transmit data is an
address after REL
signal output.
ii) REL signal is not
output, and transmit
data is a command.
Completion of reception
Serial receive disable
because of processing
Serial receive enable
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