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(2) Slave wait release (slave transmission)
Slave wait release operation is performed by WREL flag (bit 2 of interrupt timing specification register (SINT))
setting or execution of a serial I/O shift register 0 (SIO0) write instruction.
If the slave sends data, the wait is immediately released by execution of an SIO0 write instruction and the clock
rises without the start transmission bit being output in the data line. Therefore, as shown in Figure 16-48, data
should be transmitted by manipulating the P27 output latch through the program. At this time, control the low-
level width ("a" in Figure 16-48) of the first serial clock at the timing used for setting the P27 output latch to 1
after execution of an SIO0 write instruction.
In addition, if the acknowledge signal from the master is not output (if data transmission from the slave is
completed), set 1 in the WREL flag of SINT and release the wait.
For these timings, see Figure 16-46.
Master device operation
Software operation
Hardware operation
Transfer line
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Slave device operation
Software operation
Hardware operation
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries)
Figure 16-48. Slave Wait Release (Transmission)
SCL
SDA0 (SDA1)
A0
Writing
FFH
to SIO0
Setting
Setting
ACKD
CSIIF0
9
R
ACK
P27
output
latch 0
ACK
Setting
output
CSIIF0
Serial reception
1
2
a
D7
D6
Write
P27
data
output
to SIO0
latch 1
Wait
Serial transmission
release
3
D5
401
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