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9.4.2 16-bit timer/event counter mode
When bit 2 (TMC12) of the 8-bit timer mode control register (TMC1) is set to 1, the 16-bit timer/event counter mode
is selected.
The count clocks are selected with bits 0 to 3 (TCL10 to TCL13) of timer clock select register (TCL1). The overflow
signal of 8-bit timer/event counter 1 (TM1) becomes a count clock of 8-bit timer/event counter 2 (TM2). Count operation
enable/disable is selected with bit 0 (TCE1) of TMC1.
(1) Interval timer operation
The 8-bit timer/event counter operates as interval timer which generates interrupt requests repeatedly at intervals
of the count value preset to 2-channel 8-bit compare registers (CR10 and CR20). When setting the count value,
the upper 8-bit value is set as CR20 and the lower 8-bit value as CR10. For the count value (interval time) which
can be set refer to Table 9-9.
When the 8-bit timer register 1 (TM1) and CR10 values match and the 8-bit timer register 2 (TM2) and CR20
values match, counting continues with the TM1 and TM2 values cleared to 0 and the interrupt request signal
(INTTM2) is generated. For the operation timings of the interval timer, refer to Figure 9-11.
Count clock can be selected with bits 0 to 3 (TCL10 to TCL13) of the timer clock select register 1 (TCL1). The
overflow signal of the TM1 becomes a count clock of the TM2.
Count Clock
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TMS (TM1, TM2)
Count Value
CR10, CR20
INTTM2
Interval time = (N + 1) × t : N = 0000H to FFFFH
Remark
216
CHAPTER 9 8-BIT TIMER/EVENT COUNTER
Figure 9-11. Interval Timer Operation Timings
t
0000
0001
Count Start
N
TO2
Interval Time
N
0000 0001
Clear
N
Interrupt Request
Acknowledge
Interval Time
N
0000 0001
N
Clear
N
N
Interrupt Request
Acknowledge
Interval Time
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