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DIVXU (DIVide eXtend as Unsigned)
<Operation>
Rd ÷ Rs → Rd
<Assembly-Language Format>
DIVXU Rs, Rd
<Examples>
DIVXU R0L, R1
<Operand Size>
Byte
<Description>
This instruction divides a 16-bit general register by an 8-bit general register and places the
result in the 16-bit general register. The quotient is placed in the lower byte. The remainder is
placed in the upper byte. The operation is shown schematically below.
Rd
Dividend
16
Valid results are not assured if division by zero is attempted or an overflow occurs. Division
by zero is indicated in the Zero flag. Overflow can be avoided by the coding shown on the
next page.
<Instruction Formats>
Addressing
mode
Register direct
Rs
÷
Divisor
8
Mnem.
Operands
DIVXU
Rs, Rd
<Condition Code>
I
— — — —
I: Previous value remains unchanged.
H: Previous value remains unchanged.
N: Set to "1" if the divisor is negative;
otherwise cleared to "0."
Z: Set to "1" if the divisor is zero;
otherwise cleared to "0."
V: Previous value remains unchanged.
C: Previous value remains unchanged.
(RdH)
→
Remainder
8
Instruction code
1st byte
2nd byte
5
1
rs
0 rd
74
H
N
Z
Rd
(RdL)
Quotient
8
3rd byte
4th byte
DIVXU
V
C
— —
No. of
states
14
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