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LDC (LoaD to Control register)
<Operation>
(EAs) → CCR
<Assembly-Language Format>
LDC <EAs>, CCR
<Examples>
LDC #H'80, CCR
LDC R4H, CCR
<Operand Size>
Byte
<Description>
This instruction loads the source operand contents into the condition code register (CCR). The
source operand can be an 8-bit general register or 8-bit immediate data. Bits 4 and 6 are
loaded as well as the flag bits.
No interrupt requests are accepted immediately after this instruction. All interrupts, including
the nonmaskable interrupt (NMI), are deferred until after the next instruction.
<Instruction Formats>
Addressing
mode
Immediate
Register direct
Mnem.
Operands
LDC
#xx:8, CCR
LDC
Rs, CCR
<Condition Code>
I
I: Loaded from the source operand.
H: Loaded from the source operand.
N: Loaded from the source operand.
Z: Loaded from the source operand.
V: Loaded from the source operand.
C: Loaded from the source operand.
Instruction code
1st byte
2nd byte
0
7
IMM
0
3
0
rs
81
H
N
Z
3rd byte
4th byte
LDC
V
C
No. of
states
2
2
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