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Section 1. CPU...................................................................................................
1.1 General CPU Architecture............................................................................................... 2
1.2 Registers .......................................................................................................................... 5
1.3 Instructions ...................................................................................................................... 8
ADD (ADD binary) (byte) .............................................................................................. 37
ADD (ADD binary) (word) ............................................................................................. 38
ADDS (ADD with Sign extension) ................................................................................. 39
ADDX (ADD with eXtend carry) ................................................................................... 40
AND (AND logical) ........................................................................................................ 41
ANDC (AND Control register) ....................................................................................... 42
BAND (Bit AND) ........................................................................................................... 43
Bcc (Branch conditionally) ............................................................................................. 44
BCLR (Bit CLeaR).......................................................................................................... 47
BIAND (Bit Invert AND)................................................................................................ 49
BILD (Bit Invert LoaD) .................................................................................................. 50
BIOR (Bit Invert OR)...................................................................................................... 51
BIST (Bit Invert STore)................................................................................................... 52
BIXOR (Bit Invert eXclusive OR) .................................................................................. 53
BLD (Bit LoaD) .............................................................................................................. 54
BNOT (Bit NOT) ............................................................................................................ 55
BOR (Bit inclusive OR) .................................................................................................. 57
BSET (Bit SET)............................................................................................................... 59
BSR (Branch to SubRoutine) .......................................................................................... 61
BST (Bit STore)............................................................................................................... 62
BTST (Bit TeST) ............................................................................................................. 63
BXOR (Bit eXclusive OR).............................................................................................. 65
CMP (CoMPare) (byte) ................................................................................................... 67
CMP (CoMPare) (word).................................................................................................. 68
DAA (Decimal Adjust Add)............................................................................................ 69
DAS (Decimal Adjust Subtract)...................................................................................... 71
DEC (DECrement) .......................................................................................................... 73
DIVXU (DIVide eXtend as Unsigned) ........................................................................... 74
EEPMOV (MOVe data to EEPROM) ............................................................................. 76
Contents
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