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1.3.4 Addressing Modes and Effective Address Calculation
Table 1-11 lists the eight addressing modes and their assembly-language notation. Each
instruction can use a specific subset of these addressing modes.
Table 1-11. Addressing Modes
No.
Mode
(1)
Register direct
(2)
Register indirect
(3)
Register indirect with 16-bit displacement
(4)
Register indirect with post-increment
Register indirect with pre-decrement
(5)
Absolute address (8 or 16 bits)
(6)
Immediate (3-, 8-, or 16-bit data)
(7)
PC-relative (8-bit displacement)
(8)
Memory indirect
(1) Register Direct—Rn: The register field of the instruction specifies an 8- or 16-bit
general register containing the operand. In most cases the general register is accessed as an 8-
bit register. Only the MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits × 8
bits), and DIVXU (16 bits ÷ 8 bits) instructions have 16-bit operands.
(2) Register indirect—@Rn: The register field of the instruction specifies a 16-bit general
register containing the address of the operand.
(3) Register Indirect with Displacement—@(d:16, Rn): This mode, which is used only in
MOV instructions, is similar to register indirect but the instruction has a second word (bytes 3
and 4) which is added to the contents of the specified general register to obtain the operand
address. For the MOV.W instruction, the resulting address must be even.
(4) Register Indirect with Post-Increment or Pre-Decrement—@Rn+ or @–Rn:
•
Register indirect with post-increment—@Rn+
The @Rn+ mode is used with MOV instructions that load register from memory.
It is similar to the register indirect mode, but the 16-bit general register specified in the
register field of the instruction is incremented after the operand is accessed. The size of
the increment is 1 or 2 depending on the size of the operand: 1 for a byte operand; 2 for a
27
Notation
Rn
@Rn
@(d:16, Rn)
@Rn+
@–Rn
@aa:8, @aa:16
#xx:3, #xx:8, #xx:16
@(d:8, PC)
@@aa:8
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