1.1 General Cpu Architecture - Renesas H8/300 Series Programming Manual

1.1 General CPU Architecture

1.1.1 Features
Table 1-1 summarizes the CPU architecture. Figures 1-1 and 1-2 show how data are
stored in registers and memory.
Table 1-1. CPU Architecture
Item
Address space
Data types
General registers
Control registers
Addressing modes
Instruction length
Notes:
1. Word data stored in memory must be stored at an even address.
2. Instructions must be stored at even addresses.
3. General register R7 is used as the stack pointer (SP).
1.1.2 Data Structure
The H8/300 CPU can process 1-bit data, 4-bit (packed BCD) data, 8-bit (byte) data, and 16-bit
(word) data.
• Bit manipulation instructions operate on 1-bit data specified as bit n (n = 0, 1, 2, ..., 7) in a
byte operand.
• All operational instructions except ADDS and SUBS can operate on byte data.
Description
64K bytes, H'0000 to H'FFFF
Bit, 4-bit (packed BCD), byte, word (2 bytes)
Sixteen 8-bit general registers (R0H, R0L, ..., R7H, R7L),
also accessible as eight 16-bit general registers (R0 to R7)
Program counter (PC)
Condition code register (CCR)
Rn
@Rn
@(d:16, Rn)
@Rn+
@–Rn
@aa:8, @aa:16
#xx:8, #xx:16
@(d:8, PC)
@@aa:8
2 or 4 bytes
Register direct
Register indirect
Register indirect with 16-bit displacement
Register indirect with post-increment
Register indirect with pre-decrement
Absolute address (8 or 16 bits)
Immediate (8-, or 16-bit data)
PC-relative (8-bit displacement)
Memory indirect
2