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Appendix B. Instruction Set List (cont.)
Mnemonic
SHAL.B Rd
SHAR.B Rd
SHLL.B Rd
SHLR.B Rd
ROTXL.B Rd
ROTXR.B Rd
ROTL.B Rd
ROTR.B Rd
BSET #xx:3,Rd
BSET #xx:3,@Rd
BSET #xx:3,@aa:8
BSET Rn,Rd
BSET Rn,@Rd
BSET Rn,@aa:8
BCLR #xx:3,Rd
BCLR #xx:3,@Rd
BCLR #xx:3,@aa:8
BCLR Rn,Rd
BCLR Rn,@Rd
BCLR Rn,@aa:8
BNOT #xx:3,Rd
BNOT #xx:3,@Rd
BNOT #xx:3,@aa:8
Operation
C
B
b
7
B
b
7
B
C
b
7
B
0
b
7
B
b
7
B
b
7
B
C
b
7
B
b
7
B (#xx:3 of Rd8) ← 1
B (#xx:3 of @Rd16) ← 1
B (#xx:3 of @aa:8) ← 1
B (Rn8 of Rd8) ← 1
B (Rn8 of @Rd16) ← 1
B (Rn8 of @aa:8) ← 1
B (#xx:3 of Rd8) ← 0
B (#xx:3 of @Rd16) ← 0
B (#xx:3 of @aa:8) ← 0
B (Rn8 of Rd8) ← 0
B (Rn8 of @Rd16) ← 0
B (Rn8 of @aa:8) ← 0
B (#xx:3 of Rd8) ← (#xx:3 of Rd8)
(#xx:3 of @Rd16) ← (#xx:3 of @Rd16)
B
(#xx:3 of @aa:8) ← (#xx:3 of @aa:8)
B
Addressing mode/
instruction length
0
2
b
0
2
C
b
0
2
0
b
0
2
C
b
0
2
b
0
2
C
b
0
2
0
b
0
2
C
b
0
2
4
2
4
2
4
2
4
2
4
120
Condition code
I
H N Z V C
◊ ◊
–
–
◊ ◊
–
–
◊ ◊
–
–
0 ◊
–
–
◊ ◊
–
–
◊ ◊
–
–
◊ ◊
–
–
◊ ◊
–
–
–
–
– –
–
–
– –
4
–
–
– –
–
–
– –
–
–
– –
4
–
–
– –
–
–
– –
–
–
– –
4
–
–
– –
–
–
– –
–
–
– –
4
–
–
– –
–
–
– –
–
–
– –
4
–
–
– –
◊
◊
2
◊
0
2
◊
0
2
◊
0
2
◊
0
2
◊
0
2
◊
0
2
◊
0
2
–
–
2
–
–
8
–
–
8
–
–
2
–
–
8
–
–
8
–
–
2
–
–
8
–
–
8
–
–
2
–
–
8
–
–
8
–
–
2
–
–
8
–
–
8
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