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Explanation: To execute the BCLR instruction, the CPU begins by reading P4DDR. Since
P4DDR is a write-only register, it is read as H'FF, even though its true value is H'3F.
Next the CPU clears bit 0 of the read data, changing the value to H'FE.
Finally, the CPU writes this value (H'FE) back to P4DDR to complete the BCLR instruction.
As a result, P4
DDR is cleared to "0," making P4
0
P4
DDR are set to "1," making P4
6
Example 2: BSET is executed to set bit 0 in the port 4 data register (P4DR) under the
following conditions.
P4
:
Input pin, Low, MOS pull-up transistor on
7
P4
:
Input pin, High, MOS pull-up transistor off
6
P4
– P4
:
Output pins, Low
5
0
The intended purpose of this BSET instruction is to switch the output level at P4
High.
Before Execution of BSET Instruction
P4
Input/output
Input
Pin state
Low
DDR
0
DR
1
Pull-up
On
Execution of BSET Instruction
BSET
#0
@PORT4
and P4
7
P4
P4
7
6
5
Input
Output Output Output Output Output Output
High
Low
0
1
0
0
Off
Off
;set bit 0 in port-4 data register
an input pin. In addition, P4
0
output pins.
6
P4
P4
4
3
Low
Low
1
1
0
0
Off
Off
18
DDR and
7
0
P4
P4
P4
2
1
Low
Low
Low
1
1
1
0
0
0
Off
Off
Off
from Low to
0
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