Renesas H8/300 Series Programming Manual page 81

DIVXU (DIVide eXtend as Unsigned)
<Note: DIVXU Overflow>
Since the DIVXU instruction performs 16-bit ÷ 8-bit → 8-bit division, an overflow will occur
if the divisor byte is equal to or less than the upper byte of the dividend. For example, H'FFFF
÷ H'01 → H'FFFF causes an overflow. (The quotient has more than 8 bits.)
Overflows can be avoided by using a subprogram like the following. A work register is
required.
To perform
DIVXU R0L, R1:
MOV.B #H'00, R2H
CMP.B R0L, R1H
BCC L1
DIVXU R0L, R1
MOV.B R1L, R2L
BRA L2
L1 MOV.B R1H, R2L
DIVXU R0L, R2
MOV.B R2H, R1H
DIVXU R0L, R1
MOV.B R2L, R2H
MOV.B R1L, R2L
L2 RTS
R1
R1
(*1)
R1
R2
(*2)
R1
(*3)
R2
R1
(*4)
R2
75
Divisor
R0L
Dividend
Remainder Quotient
Dividend
H'00
Dividend (High) (*2)
Partial remainder Dividend (Low)
Partial remainder Quotient (High)
Remainder Quotient (Low)
Quotient
DIVXU
(*1)
(*3)
(*4)