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Timer/Counter1
Prescaler
8-bit Timer/Counter0
1477G–AVR–03/05
Figure 37 shows the Timer/Counter1 prescaler. For Timer/Counter1 the clock selections
are between PCK to PCK/16384 and stop in asynchronous mode and CK to CK/16384
and stop in synchronous. The clock options are described in Table 34 on page 72 and
the Timer/Counter1 Control Register, TCCR1B. Setting the PSR1 bit in TCCR1B Regis-
ter resets the prescaler. The PCKE bit in the PLLCSR Register enables the
asynchronous mode.
Figure 37. Timer/Counter1 Prescaler
PSR1
PCKE
CK
T1CK
S
PCK
A
(64 MHz)
CS10
CS11
CS12
CS13
Figure 38 shows the block diagram for Timer/Counter0.
The 8-bit Timer/Counter0 can select clock source from CK, prescaled CK, or an external
pin. In addition, it can be stopped as described in the specification for the
Timer/Counter0 Control Register – TCCR0. The overflow status flag is found in the
Timer/Counter Interrupt Flag Register – TIFR. Control signals are found in the
Timer/Counter0 Control Register – TCCR0. The interrupt enable/disable settings for
Timer/Counter0 are found in the Timer/Counter Interrupt Mask Register – TIMSK.
When Timer/Counter0 is externally clocked, the external signal is synchronized with the
oscillator frequency of the CPU. To ensure proper sampling of the external clock, the
minimum time between two external clock transitions must be at least one internal CPU
clock period. The external clock signal is sampled on the rising edge of the internal CPU
clock.
The 8-bit Timer/Counter0 features both a high resolution and a high accuracy usage
with the lower prescaling opportunities. Similarly, the high prescaling opportunities make
the Timer/Counter0 useful for lower speed functions or exact timing functions with infre-
quent actions.
T/C PRESCALER
0
TIMER/COUNTER1 COUNT ENABLE
ATtiny26(L)
14-BIT
65
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