Watchdog Timer Control Register - Wdtcr - Atmel AVR AT90S4434 Preliminary

Figure 36. Watchdog Timer
Watchdog Timer Control Register – WDTCR
Bit 7
$21 ($41) –
Read/Write R
Initial value 0
•
Bits 7..5 – Res: Reserved Bits
These bits are reserved bits in the AT90S4434/8535 and will always read as zero.
•
Bit 4 – WDTOE: Watchdog Turn-off Enable
This bit must be set (one) when the WDE bit is cleared. Otherwise, the Watchdog will not be disabled. Once set, hardware
will clear this bit to zero after four clock cycles. Refer to the description of the WDE bit for a Watchdog disable procedure.
•
Bit 3 – WDE: Watchdog Enable
When the WDE is set (one) the Watchdog Timer is enabled and if the WDE is cleared (zero) the Watchdog Timer function
is disabled. WDE can only be cleared if the WDTOE bit is set (one). To disable an enabled Watchdog Timer, the following
procedure must be followed:
1. In the same operation, write a logical "1" to WDTOE and WDE. A logical "1" must be written to WDE even though it
is set to "1" before the disable operation starts.
2. Within the next four clock cycles, write a logical "0" to WDE. This disables the Watchdog.
•
Bits 2..0 – WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1 and 0
The WDP2, WDP1 and WDP0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled. The
different prescaling values and their corresponding time-out periods are shown in Table 22.
AT90S/LS4434 and AT90S/LS8535
46
Oscillator
1 MHz at V = 5V
CC
350 kHz at V = 3V
CC
6 5 4
– – WDTOE
R R R/W
0 0 0
3 2 1
WDE WDP2 WDP1
R/W R/W R/W
0 0 0
0
WDP0 WDTCR
R/W
0