Revision History - Xilinx Virtex-7 FPGA VC7215 Getting Started Manual

Revision History

The following table shows the revision history for this document.
Date Version
07/10/2013 1.0
10/31/2013 2.0
12/18/2013 3.0
04/16/2014 4.0
06/12/2014 5.0
10/08/2014 6.0
11/24/2014 7.0
04/27/2015 2015.1
VC7215 Getting Started Guide
UG970 (Vivado Design Suite v2015.1) April 27, 2015
Initial Xilinx release.
Updated for Vivado® Design Suite 2013.3. Updated most figures in
VC7215 IBERT Getting Started
File Hierarchy. Figure 1-31, Synthesize Out-Of-Context Module was deleted. The
name of the project files ZIP file changed to
rdf0294-vc7215-ibert-2013-3.zip. Updated
Resources and Legal Notices
Updated for Vivado Design Suite 2013.4. Updated
Figure 1-15. Updated Figure
Figure 1-28.
Updated for Vivado Design Suite 2014.1. Updated most graphics in Chapter 1
from Figure 1-10 on. File lists changed under
project file name changed to rdf0294-vc7215-ibert-2014-1.zip. The
section Launching Vivado Design Suite was changed to
Suite. The section In Case of RX Bit Errors
Updated for Vivado Design Suite 2014.2. Updated
Figure 1-19, Figure 1-20,
Figure 1-33, and Figure 1-35. Updated
Updated for Vivado Design Suite 2014.3. Updated
Figure 1-19, Figure 1-21, Figure
programming information to
C_USER_SCAN_CHAIN* was changed to 3 in
of RX Bit Errors.
Updated for Vivado Design Suite 2014.4. The name of the project files ZIP file
changed to rdf0294-vc7215-ibert-2014-4.zip. Updated
Figure 1-19, and Figure 1-23.
Updated for Vivado Design Suite 2015.1. The ZIP project file name changed to
rdf0294-vc7215-ibert-2015-1.zip. Updated
Figure 1-15, Figure 1-17,
Version changed to match the software release.
www.xilinx.com
Revision
Guide. Figure 1-30 was renamed Design Sources
links.
1-19, Figure 1-20, Figure
Extracting the Project
was added.
Figure 1-23, Figure 1-27,
Viewing GTH Transceiver
1-23, Figure 1-27, and
Starting the SuperClock-2
Figure 1-18, Figure 1-20,
Chapter 1,
Appendix A, Additional
Figure 1-10 through
1-23, Figure 1-27, and
Files. The ZIP
Setting Up Vivado Design
Figure 1-10, Figure 1-11,
Figure 1-30, Figure 1-32,
Operation.
Figure 1-10, Figure 1-11,
Figure 1-33. Added device
Module. Updated In Case
Figure 1-33.
Figure 1-10,
Figure 1-4, Figure 1-10,
Figure 1-23, and Figure 1-27.
2