Microcontroller; Figure 12.1. Cip-51 Block Diagram - Silicon Laboratories C8051T620 Manual

C8051T620/1/6/7 & C8051T320/1/2/3
12. CIP-51 Microcontroller
The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the
MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop soft-
ware. The MCU family has a superset of all the peripherals included with a standard 8051. The CIP-51
also includes on-chip debug hardware (see description in Section 30), and interfaces directly with the ana-
log and digital subsystems providing a complete data acquisition or control-system solution in a single inte-
grated circuit.
The CIP-51 Microcontroller core implements the standard 8051 organization and peripherals as well as
additional custom peripherals and functions to extend its capability (see Figure 12.1 for a block diagram).
The CIP-51 includes the following features:
 Fully Compatible with MCS-51 Instruction Set
 48 MIPS Peak Throughput with 48 MHz Clock
 0 to 48 MHz Clock Frequency
 Extended Interrupt Handler
Performance
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the stan-
dard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system
clock cycles to execute, and usually have a maximum system clock of 12 MHz. By contrast, the CIP-51
core executes 70% of its instructions in one or two system clock cycles, with no instructions taking more
than eight system clock cycles.
66
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DATA BUS
ACCUMULATOR
TMP1 TMP2
PSW
ALU
DATA BUS
BUFFER
D8
DATA POINTER
D8
PC INCREMENTER
PROGRAM COUNTER (PC)
PRGM. ADDRESS REG.
A16
PIPELINE
CONTROL
RESET
LOGIC
CLOCK
STOP
POWER CONTROL
D8
IDLE
REGISTER

Figure 12.1. CIP-51 Block Diagram

Rev. 1.2
Reset Input
Power Management Modes
On-chip Debug Logic
Program and Data Memory Security
B REGISTER STACK POINTER
SRAM
ADDRESS SRAM
REGISTER
SFR_ADDRESS
SFR_CONTROL
SFR
BUS
D8
SFR_WRITE_DATA
INTERFACE
SFR_READ_DATA
MEM_ADDRESS
D8
MEM_CONTROL
MEMORY
MEM_WRITE_DATA
INTERFACE
MEM_READ_DATA
D8
SYSTEM_IRQs
INTERRUPT
INTERFACE
EMULATION_IRQ
D8