Sfr Definition 11.1. Reg01Cn: Voltage Regulator Control - Silicon Laboratories C8051T620 Manual

SFR Definition 11.1. REG01CN: Voltage Regulator Control

Bit 7
REG0DIS VBSTAT
Name
R/W
Type
0
Reset
SFR Address = 0xC9
Bit Name
7 REG0DIS
Voltage Regulator (REG0) Disable.
This bit enables or disables the REG0 Voltage Regulator.
0: Voltage Regulator Enabled.
1: Voltage Regulator Disabled.
6 VBSTAT
VBUS Signal Status.
This bit indicates whether the device is connected to a USB network.
0: VBUS signal currently absent (device not attached to USB network).
1: VBUS signal currently present (device attached to USB network).
5 Reserved Must Write 0b.
4 REG0MD
Voltage Regulator (REG0) Mode Select.
This bit selects the Voltage Regulator mode for REG0. When REG0MD is set to 1, the REG0
voltage regulator operates in lower power (suspend) mode.
0: REG0 Voltage Regulator in normal mode.
1: REG0 Voltage Regulator in low power mode.
3 STOPCF
Stop Mode Configuration (REG1).
This bit configures the REG1 regulator's behavior when the device enters STOP mode.
0: REG1 Regulator is still active in STOP mode. Any enabled reset source will reset the device.
1: REG1 Regulator is shut down in STOP mode. Only the RST pin or power cycle can reset the
device.
2 Reserved Must Write 0b.
1 REG1MD
Voltage Regulator (REG1) Mode.
This bit selects the Voltage Regulator mode for REG1. When REG1MD is set to 1, the REG1
voltage regulator operates in lower power mode.
0: REG1 Voltage Regulator in normal mode.
1: REG1 Voltage Regulator in low power mode.
Note: This bit should not be set to '1' if the REG0 Voltage Regulator is disabled.
0 MPCE Memory Power Controller Enable.
This bit can help the system save power at slower system clock frequencies (about 2.0 MHz or
less) by automatically shutting down the EPROM memory between clocks when information is
not being fetched from the EPROM memory. This bit has no effect when the prefetch engine is
enabled.
0: Normal Mode - Memory power controller disabled (EPROM memory is always on).
1: Low Power Mode - Memory power controller enabled (EPROM turns on/off as needed).
Note: If an external clock source is used with the Memory Power Controller enabled, and the
clock frequency changes from slow (< 2.0 MHz) to fast (> 2.0 MHz), up to 20 clocks may
be "skipped" to ensure that the EPROM power is stable before reading memory.
C8051T620/1/6/7 & C8051T320/1/2/3
6 5 4
Reserved REG0MD
R R/W R/W
0 0 0
Rev. 1.2
3 2
STOPCF Reserved
R/W R/W
0 0
Function
1 0
REG1MD MPCE
R/W R/W
0 0
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