Sfr Definition 17.6. Eip2: Extended Interrupt Priority 2 - Silicon Laboratories C8051T620 Manual

SFR Definition 17.6. EIP2: Extended Interrupt Priority 2

Bit 7
Name
Type R R
Reset 0
SFR Address = 0xF7
Bit Name
7:5 Unused Read = 0000b, Write = Don't Care.
4 Reserved Must Write 0b.
3 PMAT
Port Match Interrupt Priority Control.
This bit sets the priority of the Port Match Event interrupt.
0: Port Match interrupt set to low priority level.
1: Port Match interrupt set to high priority level.
2 Reserved Must Write 0b.
1 PS1
UART1 Interrupt Priority Control.
This bit sets the priority of the UART1 interrupt.
0: UART1 interrupt set to low priority level.
1: UART1 interrupt set to high priority level.
0 PVBUS
VBUS Level Interrupt Priority Control.
This bit sets the priority of the VBUS interrupt.
0: VBUS interrupt set to low priority level.
1: VBUS interrupt set to high priority level.
C8051T620/1/6/7 & C8051T320/1/2/3
6 5 4
Reserved
R R/W
0 0 0
Rev. 1.2
3 2
PMAT Reserved
R/W R/W
0 0
Function
1 0
PS1 PVBUS
R/W R/W
0 0
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