Port Match; Sfr Definition 22.3. Xbr2: Port I/O Crossbar Register 2 - Silicon Laboratories C8051T620 Manual

SFR Definition 22.3. XBR2: Port I/O Crossbar Register 2

Bit 7
Name
Type R
Reset 0
SFR Address = 0xE3
Bit Name
7:2 Unused Read = 0000000b; Write = Don't Care.
1 Reserved Must write 0.
0 URT1E UART1 I/O Output Enable Bit.
0: UART1 I/O unavailable at Port pins.
1: UART1 TX1, RX1 routed to Port pins.

22.5. Port Match

Port match functionality allows system events to be triggered by a logic value change on P0 or P1. A soft-
ware controlled value stored in the PnMATCH registers specifies the expected or normal logic values of P0
and P1. A Port mismatch event occurs if the logic levels of the Port's input pins no longer match the soft-
ware controlled value. This allows Software to be notified if a certain change or pattern occurs on P0 or P1
input pins regardless of the XBRn settings.
The PnMASK registers can be used to individually select which P0 and P1 pins should be compared
against the PnMATCH registers. A Port mismatch event is generated if (P0 & P0MASK) does not equal
(P0MATCH & P0MASK) or if (P1 & P1MASK) does not equal (P1MATCH & P1MASK).
A Port mismatch event may be used to generate an interrupt or wake the device from a low power mode,
such as IDLE or SUSPEND. See the Interrupts and Power Options chapters for more details on interrupt
and wake-up sources.
C8051T620/1/6/7 & C8051T320/1/2/3
6 5 4
R R R
0 0 0
Rev. 1.2
3 2
Reserved
R R
0 0
Function
1 0
URT1E
R/W R/W
0 0
149