Silicon Laboratories C8051T620 Manual

Silicon Laboratories C8051T620 Manual

Full speed usb eprom mcu family
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Analog Peripherals
-
10-Bit ADC ('T620/6/7 and 'T320/1 only)
Up to 500 ksps
Up to 21 external inputs
VREF from on-chip VREF, external pin, Internal 1.8 V
Regulator or V
Internal or external start of conversion source
Built-in temperature sensor
-
Comparators
Programmable hysteresis and response time
Configurable as interrupt or reset source
Low current (<0.5 µA)
USB Function Controller
-
USB specification 2.0 compliant
-
Full speed (12 Mbps) or low speed (1.5 Mbps) oper-
ation
-
Integrated clock recovery; no external oscillator
required for full speed or low speed
-
Supports eight flexible endpoints
-
1 kB USB buffer memory
-
Integrated transceiver; no external resistors
required
On-Chip Debug
-
C8051F34A can be used as code development plat-
form; Complete development kit available
-
On-chip debug circuitry facilitates full speed, non-
intrusive in-system debug
Provides breakpoints, single stepping, 
-
inspect/modify memory and registers
Supply Voltage 1.8 to 5.25 V
-
On-chip LDO for internal core supply
-
Built-in supply voltage monitor
Rev. 1.2 7/12
C8051T620/1/6/7 & C8051T320/1/2/3
DD
ANALOG
PERIPHERALS
A
10-bit
M
500 ksps
U
ADC
X
TEMP
SENSOR
LOW FREQUENCY INTERNAL
OSCILLATOR
48 MHz PRECISION INTERNAL
OSCILLATOR
HIGH-SPEED CONTROLLER CORE
64 kB
EPROM
FLEXIBLE
INTERRUPTS
Copyright © 2012 by Silicon Laboratories
Full Speed USB EPROM MCU Family
High-Speed 8051 µC Core
-
Pipelined instruction architecture; executes 70% of
instructions in 1 or 2 system clocks
-
Up to 48 MIPS throughput with 48 MHz clock
-
Expanded interrupt handler
Memory
-
Up to 3328 bytes internal data RAM (256 + up to
3072)
-
Up to 64 kB byte-programmable EPROM code
memory
-
EPROM can be programmed from firmware running
on the device
Digital Peripherals
-
25 Port I/O with high sink current capability
-
Hardware enhanced SPI™, SMBus™, and two
enhanced UART serial ports
-
Four general purpose 16-bit counter/timers
-
16-Bit programmable counter array (PCA) with five
capture/compare modules and enhanced PWM
functionality
Clock Sources
-
Two internal oscillators:
48 MHz: ±0.25% accuracy with clock recovery
enabled. Supports all USB and UART modes
80/40/20/10 kHz low frequency, low power
-
External oscillator: Crystal, RC, C, or CMOS Clock
-
Can switch between clock sources on-the-fly; useful
in power saving modes
Package Options:
-
5 x 5 mm QFN28 or QFN32
-
9 x 9 mm LQFP32
Temperature Range: –40 to +85 °C
DIGITAL I/O
UART0
UART1
SMBus
VREF
SPI
PCA
Timer 0
+
+
Timer 1
-
-
Timer 2
VOLTAGE
Timer 3
COMPARATORS
USB Controller /
Transceiver
8051 CPU
3328 B SRAM
(48 MIPS)
DEBUG CIRCUITRY
POR
Port 0
Port 1
Port 2
P3.0
WDT
C8051T620/1/6/7 & C8051T320/1/2/3

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Summary of Contents for Silicon Laboratories C8051T620

  • Page 1 LOW FREQUENCY INTERNAL OSCILLATOR USB Controller / Transceiver 48 MHz PRECISION INTERNAL OSCILLATOR HIGH-SPEED CONTROLLER CORE 64 kB 8051 CPU 3328 B SRAM EPROM (48 MIPS) FLEXIBLE DEBUG CIRCUITRY INTERRUPTS Rev. 1.2 7/12 Copyright © 2012 by Silicon Laboratories C8051T620/1/6/7 & C8051T320/1/2/3...
  • Page 2 C8051T620/1/6/7 & C8051T320/1/2/3 Rev. 1.2...
  • Page 3: Table Of Contents

    7.1. Absolute Maximum Specifications..............34 7.2. Electrical Characteristics ................... 35 7.3. Typical Performance Curves ................44 8. 10-Bit ADC (ADC0, C8051T620/6/7 and C8051T320/1 Only) ......... 45 8.1. Output Code Formatting ..................46 8.2. 8-Bit Mode ......................46 8.3. Modes of Operation ................... 46 8.3.1.
  • Page 4 C8051T620/1/6/7 & C8051T320/1/2/3 15.2.1.2. Bit Addressable Locations .............. 90 15.2.1.3. Stack .................... 90 15.2.2. External RAM ..................91 15.2.3. Accessing USB FIFO Space ..............91 16. Special Function Registers................... 95 17. Interrupts ......................101 17.1. MCU Interrupt Sources and Vectors.............. 102 17.1.1.
  • Page 5 C8051T620/1/6/7 & C8051T320/1/2/3 21.6. External Oscillator Drive Circuit..............134 21.6.1. External Crystal Mode................134 21.6.2. External RC Example................136 21.6.3. External Capacitor Example..............136 22. Port Input/Output ....................138 22.1. Port I/O Modes of Operation................139 22.1.1. Port Pins Configured for Analog I/O............139 22.1.2.
  • Page 6 C8051T620/1/6/7 & C8051T320/1/2/3 24.3.1. Transmitter Vs. Receiver............... 196 24.3.2. Arbitration....................196 24.3.3. Clock Low Extension................196 24.3.4. SCL Low Timeout.................. 196 24.3.5. SCL High (SMBus Free) Timeout ............197 24.4. Using the SMBus................... 197 24.4.1. SMBus Configuration Register.............. 197 24.4.2. SMB0CN Control Register ..............201 24.4.2.1.
  • Page 7 C8051T620/1/6/7 & C8051T320/1/2/3 28. Timers ........................246 28.1. Timer 0 and Timer 1 ..................248 28.1.1. Mode 0: 13-bit Counter/Timer ............... 248 28.1.2. Mode 1: 16-bit Counter/Timer ............... 249 28.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload........249 28.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)........ 250 28.2.
  • Page 8 Figure 15.2. C8051T626/7 Memory Map ..............88 Figure 15.3. Program Memory Map ................. 89 Figure 15.4. C8051T620/1 and C8051T320/1/2/3 USB FIFO Space and  XRAM Memory Map with USBFAE Set to 1 ............92 Figure 15.5. C8051T626/7 USB FIFO Space and XRAM Memory Map ...
  • Page 9 Figure 23.1. USB0 Block Diagram ................. 160 Figure 23.2. USB0 Register Access Scheme ............163 Figure 23.3. C8051T620/1 and C8051T320/1/2/3 USB FIFO Allocation ....169 Figure 23.4. C8051T626/7 USB FIFO Allocation ..........170 Figure 24.1. SMBus Block Diagram ..............194 Figure 24.2.
  • Page 10 C8051T620/1/6/7 & C8051T320/1/2/3 Figure 27.11. SPI Slave Timing (CKPHA = 1) ............244 Figure 28.1. T0 Mode 0 Block Diagram ..............249 Figure 28.2. T0 Mode 2 Block Diagram ..............250 Figure 28.3. T0 Mode 3 Block Diagram ..............251 Figure 28.4.
  • Page 11 C8051T620/1/6/7 & C8051T320/1/2/3 List of Tables Table 2.1. Product Selection Guide ................. 21 Table 3.1. Pin Definitions for the C8051T620/1/6/7 & C8051T320/1/2/3 ....22 Table 7.1. Absolute Maximum Ratings ..............34 Table 7.2. Global Electrical Characteristics ............. 35 Table 7.3. Port I/O DC Electrical Characteristics ............. 36 Table 7.4.
  • Page 12 C8051T620/1/6/7 & C8051T320/1/2/3 List of Registers SFR Definition 8.1. ADC0CF: ADC0 Configuration ............49 SFR Definition 8.2. ADC0H: ADC0 Data Word MSB ............ 50 SFR Definition 8.3. ADC0L: ADC0 Data Word LSB ............50 SFR Definition 8.4. ADC0CN: ADC0 Control ..............51 SFR Definition 8.5.
  • Page 13 C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 21.5. OSCLCN: Internal L-F Oscillator Control ........133 SFR Definition 21.6. OSCXCN: External Oscillator Control ........137 SFR Definition 22.1. XBR0: Port I/O Crossbar Register 0 .......... 147 SFR Definition 22.2. XBR1: Port I/O Crossbar Register 1 .......... 148 SFR Definition 22.3.
  • Page 14 C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 28.2. TCON: Timer Control ..............252 SFR Definition 28.3. TMOD: Timer Mode ..............253 SFR Definition 28.4. TL0: Timer 0 Low Byte ............... 254 SFR Definition 28.5. TL1: Timer 1 Low Byte ............... 254 SFR Definition 28.6. TH0: Timer 0 High Byte ............. 255 SFR Definition 28.7.
  • Page 15: System Overview

    USB communication. An additional internal LDO is used to supply the processor core voltage at 1.8 V. The Port I/O and RST pins are tolerant of input signals up to 5 V. The C8051T620/1/6/7 are available in 32-pin QFN packaging, the C8051T320/2 are available in 32-pin LQFP packaging, and the C8051T321/3 are available in 28-pin QFN packaging.
  • Page 16: Figure 1.1. C8051T620/1 Block Diagram

    Voltage Internal Oscillator Reference VREF VREF Clock Low Freq. Recovery Oscillator VREF 10-bit 500ksps Temp USB Peripheral Sensor Controller Full / Low CP0, CP0A Speed 1k Byte Transceiver CP1, CP1A VBUS 2 Comparators Figure 1.1. C8051T620/1 Block Diagram Rev. 1.2...
  • Page 17: Figure 1.2. C8051T626/7 Block Diagram

    C8051T620/1/6/7 & C8051T320/1/2/3 Power On Port I/O Configuration CIP-51 8051 Reset P0.0 Controller Core Digital Peripherals P0.1 Reset 64/32k Byte OTP P0.2/XTAL1 UART0 Program Memory P0.3/XTAL2 Port 0 Debug / C2CK/RST UART1 Drivers P0.4/TX Programming P0.5/RX Hardware 256 Byte SRAM Timers 0, P0.6/CNVSTR...
  • Page 18: Figure 1.3. C8051T320/2 Block Diagram

    C8051T620/1/6/7 & C8051T320/1/2/3 Port I/O Configuration Power On CIP-51 8051 Reset P0.0 Controller Core Digital Peripherals P0.1 Reset 16k Byte OTP P0.2/XTAL1 UART0 Program Memory P0.3/XTAL2 Port 0 Debug / C2CK/RST UART1 Drivers P0.4/TX Programming P0.5/RX Hardware 256 Byte SRAM Timers 0, P0.6/CNVSTR...
  • Page 19: Figure 1.4. C8051T321/3 Block Diagram

    C8051T620/1/6/7 & C8051T320/1/2/3 Port I/O Configuration Power On CIP-51 8051 Reset P0.0 Controller Core Digital Peripherals P0.1 Reset 16k Byte OTP P0.2/XTAL1 UART0 Program Memory Port 0 P0.3/XTAL2 Debug / C2CK/RST UART1 Drivers P0.4/TX Programming P0.5/RX Hardware 256 Byte SRAM Timers 0, P0.6/CNVSTR...
  • Page 20: Figure 1.5. Typical Bus-Powered Connections

    C8051T620/1/6/7 & C8051T320/1/2/3 1.8V to VDD VIO* VIO can be connected directly VIO* to VDD. SUPPLY NET Add decoupling/bypass 4.7µF 0.1µF RESET SIGNAL capacitors close to each A 1-5 kohm pull-up resistor can kohm RST/ voltage supply pin. be connected to VIO* for added C2CK noise immunity.
  • Page 21: Ordering Information

    C8051T620/1/6/7 & C8051T320/1/2/3 2. Ordering Information Table 2.1. Product Selection Guide C8051T620-GM 48 16k 1280 Y Y 24 Y QFN32 C8051T621-GM 48 16k 1280 Y Y 24 — — — 2 QFN32 C8051T626-B-GM 48 64k 3328 Y Y 24 Y...
  • Page 22: Pin Definitions

    C8051T620/1/6/7 & C8051T320/1/2/3 3. Pin Definitions Table 3.1. Pin Definitions for the C8051T620/1/6/7 & C8051T320/1/2/3 Pin Number Name Type Description ‘T62x ‘T320/2 ‘T321/3 Power Supply Voltage. Ground. RST/ D I/O Device Reset. Open-drain output of internal POR or monitor. An external source can initiate a system reset by driving this pin low for at least 10 µs.
  • Page 23 C8051T620/1/6/7 & C8051T320/1/2/3 Table 3.1. Pin Definitions for the C8051T620/1/6/7 & C8051T320/1/2/3(Continued) Pin Number Name Type Description ‘T62x ‘T320/2 ‘T321/3 P0.3/ D I/O or Port 0.3. A In XTAL2 A Out External Clock Output. This pin is the excitation driver for an external crystal or resonator.
  • Page 24 C8051T620/1/6/7 & C8051T320/1/2/3 Table 3.1. Pin Definitions for the C8051T620/1/6/7 & C8051T320/1/2/3(Continued) Pin Number Name Type Description ‘T62x ‘T320/2 ‘T321/3 P1.5/ D I/O or Port 1.5. A In A In Programming Supply Voltage P1.6 D I/O or Port 1.6. A In P1.7...
  • Page 25: Figure 3.1. Qfn-32 Pinout Diagram (Top View)

    C8051T620/1/6/7 & C8051T320/1/2/3 P0.1 P1.2 P0.0 P1.3 P1.4 P1.5 / VPP C8051T620/1/6/7-GM Top View P1.6 P1.7 P2.0 GND (optional) REGIN P2.1 Figure 3.1. QFN-32 Pinout Diagram (Top View) Rev. 1.2...
  • Page 26: Figure 3.2. Lqfp-32 Pinout Diagram (Top View)

    C8051T620/1/6/7 & C8051T320/1/2/3 P1.2 P0.1 P1.3 P0.0 P1.4 C8051T320/2-GQ P1.5 / VPP Top View P1.6 P1.7 REGIN P2.0 VBUS P2.1 Figure 3.2. LQFP-32 Pinout Diagram (Top View) Rev. 1.2...
  • Page 27: Figure 3.3. Qfn-28 Pinout Diagram (Top View)

    C8051T620/1/6/7 & C8051T320/1/2/3 P0.1 P1.1 P0.0 P1.2 P1.3 C8051T321/3-GM P1.4 Top View P1.5 / VPP P1.6 GND (optional) REGIN P1.7 Figure 3.3. QFN-28 Pinout Diagram (Top View) Rev. 1.2...
  • Page 28: Lqfp-32 Package Specifications

    C8051T620/1/6/7 & C8051T320/1/2/3 4. LQFP-32 Package Specifications Figure 4.1. LQFP-32 Package Drawing Table 4.1. LQFP-32 Package Dimensions Dimension Dimension — — 1.60 9.00 BSC. 0.05 — 0.15 7.00 BSC. 1.35 1.40 1.45 0.45 0.60 0.75 0.30 0.37 0.45 0.20 0.09 —...
  • Page 29: Figure 4.2. Lqfp-32 Recommended Pcb Land Pattern

    C8051T620/1/6/7 & C8051T320/1/2/3 Figure 4.2. LQFP-32 Recommended PCB Land Pattern Table 4.2. LQFP-32 PCB Land Pattern Dimensions Dimension Dimension 8.40 8.50 0.40 0.50 8.40 8.50 1.25 1.35 0.80 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted.
  • Page 30: Package Specifications

    C8051T620/1/6/7 & C8051T320/1/2/3 5. QFN-32 Package Specifications Figure 5.1. QFN-32 Package Drawing Table 5.1. QFN-32 Package Dimensions Dimension Dimension 0.80 0.90 1.00 3.20 3.30 3.40 0.00 0.02 0.05 0.30 0.40 0.50 0.18 0.25 0.30 0.00 — 0.15 5.00 BSC. 0.15 3.20...
  • Page 31: Figure 5.2. Qfn-32 Recommended Pcb Land Pattern

    C8051T620/1/6/7 & C8051T320/1/2/3 Figure 5.2. QFN-32 Recommended PCB Land Pattern Table 5.2. QFN-32 PCB Land Pattern Dimensions Dimension Dimension 4.80 4.90 3.20 3.40 4.80 4.90 0.75 0.85 0.50 BSC 3.20 3.40 0.20 0.30 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted.
  • Page 32: Package Specifications

    C8051T620/1/6/7 & C8051T320/1/2/3 6. QFN-28 Package Specifications Figure 6.1. QFN-28 Package Drawing Table 6.1. QFN-28 Package Dimensions Dimension Dimension 0.80 0.90 1.00 0.35 0.55 0.65 0.00 0.02 0.05 0.00 — 0.15 0.25 REF 0.15 0.18 0.23 0.30 0.10 5.00 BSC.
  • Page 33: Figure 6.2. Qfn-28 Recommended Pcb Land Pattern

    C8051T620/1/6/7 & C8051T320/1/2/3 Figure 6.2. QFN-28 Recommended PCB Land Pattern Table 6.2. QFN-28 PCB Land Pattern Dimensions Dimension Dimension 4.80 3.20 3.30 4.80 0.85 0.95 0.50 3.20 3.30 0.20 0.30 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted.
  • Page 34: Electrical Characteristics

    C8051T620/1/6/7 & C8051T320/1/2/3 7. Electrical Characteristics 7.1. Absolute Maximum Specifications Table 7.1. Absolute Maximum Ratings Parameters Test Condition Unit Ambient temperature under bias –55 — °C Storage Temperature –65 — °C Voltage on RST or any Port I/O > 2.2 V –0.3...
  • Page 35: Electrical Characteristics

    C8051T620/1/6/7 & C8051T320/1/2/3 7.2. Electrical Characteristics Table 7.2. Global Electrical Characteristics –40 to +85 °C, 25 MHz system clock unless otherwise specified. Parameters Test Condition Unit Supply Voltage (Note 1) Regulator1 in Normal Mode Regulator1 in Bypass Mode 1.75 —...
  • Page 36: Table 7.3. Port I/O Dc Electrical Characteristics

    C8051T620/1/6/7 & C8051T320/1/2/3 Table 7.3. Port I/O DC Electrical Characteristics = 1.8 to 3.6 V, V < V , –40 to +85 °C unless otherwise specified. Parameters Test Condition Unit Output High Voltage I = –10 µA, Port I/O push-pull –...
  • Page 37: Table 7.5. Internal Voltage Regulator Electrical Characteristics

    Notes: 1. Input range specified for regulation. When an external regulator is used, should be tied to 2. Output current is total regulator output, including any current required by the C8051T620/1/6/7 & C8051T320/1/2/3. 3. The minimum input voltage is 2.7 V or (max load), whichever is greater.
  • Page 38: Table 7.6. Eprom Electrical Characteristics

    C8051T620/1/6/7 & C8051T320/1/2/3 Table 7.6. EPROM Electrical Characteristics Parameters Test Condition Unit EPROM Size (Note 1) C8051T620/1 & C8051T320/1/2/3 16384 — — bytes C8051T626 65535 — — bytes C8051T627 32768 — — bytes Write Cycle Time (per µs Byte) (Note 2)
  • Page 39: Table 7.8. Internal Low-Frequency Oscillator Electrical Characteristics

    C8051T620/1/6/7 & C8051T320/1/2/3 Table 7.8. Internal Low-Frequency Oscillator Electrical Characteristics = 2.7 to 3.6 V; T = –40 to +85 °C unless otherwise specified; Using factory-calibrated settings. Parameters Test Condition Unit Oscillator Frequency OSCLD = 11b Oscillator Supply Current ...
  • Page 40: Table 7.10. Adc0 Electrical Characteristics

    C8051T620/1/6/7 & C8051T320/1/2/3 Table 7.10. ADC0 Electrical Characteristics – = 3.0 V, VREF = 2.40 V (REFSL=0), PGA Gain = 1, 40 to +85 °C unless otherwise specified. Parameters Test Condition Unit DC Accuracy Resolution bits Integral Nonlinearity — ±0.5 ±1...
  • Page 41: Table 7.11. Temperature Sensor Electrical Characteristics

    C8051T620/1/6/7 & C8051T320/1/2/3 Table 7.11. Temperature Sensor Electrical Characteristics – = 3.0 V, 40 to +85 °C unless otherwise specified. Parameters Test Condition Unit Linearity — ± 0.2 — °C Slope C8051T626/7/T320/1/2/3 — 2.87 — mV/°C C8051T626/7 — 2.99 —...
  • Page 42: Table 7.13. Comparator Electrical Characteristics

    C8051T620/1/6/7 & C8051T320/1/2/3 Table 7.13. Comparator Electrical Characteristics = 3.0 V, –40 to +85 °C unless otherwise noted. Parameters Test Condition Unit Response Time: CP0+ – CP0– = 100 mV — — Mode 0, Vcm = 1.5 V CP0+ – CP0– = –100 mV —...
  • Page 43: Table 7.14. Usb Transceiver Electrical Characteristics

    C8051T620/1/6/7 & C8051T320/1/2/3 Table 7.14. USB Transceiver Electrical Characteristics = 3.0 V to 3.6 V, –40 to +85 °C unless otherwise specified. Parameters Test Condition Unit Transmitter Output High Voltage (V — — Output Low Voltage (V — — Output Crossover Point —...
  • Page 44: Typical Performance Curves

    C8051T620/1/6/7 & C8051T320/1/2/3 7.3. Typical Performance Curves 12.0 10.0 = 3.3 V = 1.8 V SYSCLK (MHz) Figure 7.1. Normal Mode Digital Supply Current vs. Frequency (MPCE = 1) = 3.3 V = 1.8 V SYSCLK (MHz) Figure 7.2. Idle Mode Digital Supply Current vs. Frequency (MPCE = 1)
  • Page 45: Bit Adc (Adc0, C8051T620/6/7 And C8051T320/1 Only)

    ADC may be configured to measure various different signals using the analog multiplexer described in Section “8.5. ADC0 Analog Multiplexer (C8051T620/6/7 and C8051T320/1 Only)” on page 55. The voltage reference for the ADC is selected as described in Section “10. Voltage Reference Options” on page 59.
  • Page 46: Output Code Formatting

    C8051T620/1/6/7 & C8051T320/1/2/3 8.1. Output Code Formatting The ADC measures the input voltage with reference to GND. The registers ADC0H and ADC0L contain the high and low bytes of the output conversion code from the ADC at the completion of each conversion. Data can be right-justified or left-justified, depending on the setting of the AD0LJST bit.
  • Page 47: Tracking Modes

    C8051T620/1/6/7 & C8051T320/1/2/3 8.3.2. Tracking Modes The AD0TM bit in register ADC0CN enables "delayed conversions", and will delay the actual conversion start by three SAR clock cycles, during which time the ADC will continue to track the input. If AD0TM is left at logic 0, a conversion will begin immediately, without the extra tracking time.
  • Page 48: Settling Time Requirements

    C8051T620/1/6/7 & C8051T320/1/2/3 8.3.3. Settling Time Requirements A minimum tracking time is required before each conversion to ensure that an accurate conversion is per- formed. This tracking time is determined by any series impedance, including the AMUX0 resistance, the the ADC0 sampling capacitance, and the accuracy required for the conversion. Note that in delayed track- ing mode, three SAR clocks are used for tracking at the start of every conversion.
  • Page 49: Sfr Definition 8.1. Adc0Cf: Adc0 Configuration

    C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 8.1. ADC0CF: ADC0 Configuration AD0SC[4:0] AD0LJST AD08BE AMP0GN0 Name Type Reset SFR Address = 0xBC Name Function 7:3 AD0SC[4:0] ADC0 SAR Conversion Clock Period Bits. SAR Conversion clock is derived from system clock by the following equation, where AD0SC refers to the 5-bit value held in bits AD0SC4–0.
  • Page 50: Sfr Definition 8.2. Adc0H: Adc0 Data Word Msb

    C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 8.2. ADC0H: ADC0 Data Word MSB ADC0H[7:0] Name Type Reset SFR Address = 0xBE Name Function 7:0 ADC0H[7:0] ADC0 Data Word High-Order Bits. For AD0LJST = 0: Bits 7–2 will read 000000b. Bits 1–0 are the upper 2 bits of the 10- bit ADC0 Data Word.
  • Page 51: Sfr Definition 8.4. Adc0Cn: Adc0 Control

    C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 8.4. ADC0CN: ADC0 Control AD0EN AD0TM AD0INT AD0BUSY AD0WINT AD0CM[2:0] Name Type Reset SFR Address = 0xE8; Bit-Addressable Name Function AD0EN ADC0 Enable Bit. 0: ADC0 Disabled. ADC0 is in low-power shutdown. 1: ADC0 Enabled. ADC0 is active and ready for data conversions.
  • Page 52: Programmable Window Detector

    C8051T620/1/6/7 & C8051T320/1/2/3 8.4. Programmable Window Detector The ADC Programmable Window Detector continuously compares the ADC0 output registers to user-pro- grammed limits, and notifies the system when a desired condition is detected. This is especially effective in an interrupt-driven system, saving code space and CPU bandwidth while delivering faster system response times.
  • Page 53: Sfr Definition 8.7. Adc0Lth: Adc0 Less-Than Data High Byte

    C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 8.7. ADC0LTH: ADC0 Less-Than Data High Byte ADC0LTH[7:0] Name Type Reset SFR Address = 0xC6 Name Function ADC0LTH[7:0] ADC0 Less-Than Data Word High-Order Bits. SFR Definition 8.8. ADC0LTL: ADC0 Less-Than Data Low Byte ADC0LTL[7:0] Name...
  • Page 54: Window Detector Example

    C8051T620/1/6/7 & C8051T320/1/2/3 8.4.1. Window Detector Example Figure 8.4 shows example window comparisons right-justified data, with ADC0LTH:ADC0LTL = 0x0080 (128d) and ADC0GTH:ADC0GTL = 0x0040 (64d). The input voltage can range from 0 to VREF x (1023/1024) with respect to GND, and is represented by a 10-bit unsigned integer value.
  • Page 55: Adc0 Analog Multiplexer (C8051T620/6/7 And C8051T320/1 Only)

    8.5. ADC0 Analog Multiplexer (C8051T620/6/7 and C8051T320/1 Only) ADC0 on the C8051T620/6/7 and C8051T320/1 uses an analog input multiplexer to select the positive input to the ADC. Any of the following may be selected as the positive input: Port 1, 2, P3.0 and some Port 0 I/O pins, the on-chip temperature sensor, or the positive power supply (V ).
  • Page 56: Sfr Definition 8.9. Amx0P: Amux0 Positive Channel Select

    00110: P1.6 00111: P1.7 01000: P2.0 01001: P2.1 01010: P2.2 01011: P2.3 01100: P2.4 (C8051T320/2 and C8051T620/6/7 Only) 01101: P2.5 (C8051T320/2 and C8051T620/6/7 Only) 01110: P2.6 (C8051T320/2 and C8051T620/6/7 Only) 01111: P2.7 (C8051T320/2 Only) 10000: P3.0 10001: P0.0 10010: P0.1 10011: P0.4...
  • Page 57: Temperature Sensor (C8051T620/6/7 And C8051T320/1 Only)

    C8051T620/1/6/7 & C8051T320/1/2/3 9. Temperature Sensor (C8051T620/6/7 and C8051T320/1 Only) An on-chip temperature sensor is included on the C8051T620/6/7 and C8051T320/1 which can be directly accessed via the ADC multiplexer in single-ended configuration. To use the ADC to measure the tempera- ture sensor, the ADC mux channel should be configured to connect to the temperature sensor.
  • Page 58: Calibration

    C8051T620/1/6/7 & C8051T320/1/2/3 9.1. Calibration The uncalibrated temperature sensor output is extremely linear and suitable for relative temperature mea- surements (see Table 7.11 on page 41 for specifications). For absolute temperature measurements, offset and/or gain calibration is recommended. A single-point offset measurement of the temperature sensor is performed on each device during produc- tion test.
  • Page 59: Voltage Reference Options

    BIASE bit in register REF0CN. The electrical specifications for the voltage reference circuit are given in Table 7.12. The C8051T620/6/7 and C8051T320/1 devices also include an on-chip voltage reference circuit which consists of a 1.2 V, temperature stable bandgap voltage reference generator and a selectable-gain output buffer amplifier.
  • Page 60: Sfr Definition 10.1. Ref0Cn: Reference Control

    C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 10.1. REF0CN: Reference Control REFBGS REGOVR REFSL TEMPE BIASE REFBE Name Type Reset SFR Address = 0xD1 Name Function REFBGS Reference Buffer Gain Select. This bit selects between 1x and 2x gain for the on-chip voltage reference buffer.
  • Page 61: Voltage Regulators (Reg0 And Reg1)

    11. Voltage Regulators (REG0 and REG1) C8051T620/1/6/7 & C8051T320/1/2/3 devices include two internal voltage regulators: one regulates a volt- age source on REGIN to 3.45 V (REG0), and the other regulates the internal core supply to 1.8 V from a supply of 1.8 to 3.6 V (REG1).
  • Page 62: Figure 11.2. Reg0 Configuration: Usb Self-Powered

    C8051T620/1/6/7 & C8051T320/1/2/3 VBUS From VBUS VBUS Sense From 5 V REGIN 5 V In Voltage Regulator (REG0) Power Net 3 V Out To 3 V Device Power Net Power Net Figure 11.2. REG0 Configuration: USB Self-Powered VBUS From VBUS...
  • Page 63: Figure 11.4. Reg0 Configuration: No Usb Connection

    C8051T620/1/6/7 & C8051T320/1/2/3 VBUS VBUS Sense From 5 V REGIN 5 V In Voltage Regulator (REG0) Power Net 3 V Out To 3 V Device Power Net Power Net Figure 11.4. REG0 Configuration: No USB Connection Rev. 1.2...
  • Page 64: Voltage Regulator (Reg1)

    C8051T620/1/6/7 & C8051T320/1/2/3 11.2. Voltage Regulator (REG1) Under default conditions, the internal REG1 regulator will remain on when the device enters STOP mode. This allows any enabled reset source to generate a reset for the device and bring the device out of STOP mode.
  • Page 65: Sfr Definition 11.1. Reg01Cn: Voltage Regulator Control

    C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 11.1. REG01CN: Voltage Regulator Control REG0DIS VBSTAT Reserved REG0MD STOPCF Reserved REG1MD MPCE Name Type Reset SFR Address = 0xC9 Name Function REG0DIS Voltage Regulator (REG0) Disable. This bit enables or disables the REG0 Voltage Regulator.
  • Page 66: Microcontroller

    C8051T620/1/6/7 & C8051T320/1/2/3 12. CIP-51 Microcontroller The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop soft- ware. The MCU family has a superset of all the peripherals included with a standard 8051. The CIP-51...
  • Page 67: Instruction Set

    C8051T620/1/6/7 & C8051T320/1/2/3 With the CIP-51's maximum system clock at 48 MHz, it has a peak throughput of 48 MIPS. The CIP-51 has a total of 109 instructions. The table below shows the total number of instructions that require each execu- tion time.
  • Page 68: Table 12.1. Cip-51 Instruction Set Summary

    C8051T620/1/6/7 & C8051T320/1/2/3 Table 12.1. CIP-51 Instruction Set Summary Mnemonic Description Bytes Clock Cycles Arithmetic Operations ADD A, Rn Add register to A ADD A, direct Add direct byte to A ADD A, @Ri Add indirect RAM to A ADD A, #data...
  • Page 69 C8051T620/1/6/7 & C8051T320/1/2/3 Table 12.1. CIP-51 Instruction Set Summary(Continued) Mnemonic Description Bytes Clock Cycles ORL A, direct OR direct byte to A ORL A, @Ri OR indirect RAM to A ORL A, #data OR immediate to A ORL direct, A...
  • Page 70 C8051T620/1/6/7 & C8051T320/1/2/3 Table 12.1. CIP-51 Instruction Set Summary(Continued) Mnemonic Description Bytes Clock Cycles MOV DPTR, #data16 Load DPTR with 16-bit constant MOVC A, @A+DPTR Move code byte relative DPTR to A MOVC A, @A+PC Move code byte relative PC to A...
  • Page 71 C8051T620/1/6/7 & C8051T320/1/2/3 Table 12.1. CIP-51 Instruction Set Summary(Continued) Mnemonic Description Bytes Clock Cycles Return from subroutine RETI Return from interrupt AJMP addr11 Absolute jump LJMP addr16 Long jump SJMP rel Short jump (relative address) JMP @A+DPTR Jump indirect relative to DPTR...
  • Page 72 C8051T620/1/6/7 & C8051T320/1/2/3 Notes on Registers, Operands and Addressing Modes: Rn - Register R0–R7 of the currently selected register bank. @Ri - Data RAM location addressed indirectly through R0 or R1. rel - 8-bit, signed (two’s complement) offset relative to the first byte of the following instruction. Used by SJMP and all conditional jumps.
  • Page 73: Register Descriptions

    C8051T620/1/6/7 & C8051T320/1/2/3 12.2. CIP-51 Register Descriptions Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits should always be written to the value indicated in the SFR description. Future product versions may use these bits to implement new features in which case the reset value of the bit will be the indicated value, selecting the feature's default state.
  • Page 74: Sfr Definition 12.3. Sp: Stack Pointer

    C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 12.3. SP: Stack Pointer Name SP[7:0] Type Reset SFR Address = 0x81 Name Function SP[7:0] Stack Pointer. The Stack Pointer holds the location of the top of the stack. The stack pointer is incre- mented before every PUSH operation. The SP register defaults to 0x07 after reset.
  • Page 75: Sfr Definition 12.6. Psw: Program Status Word

    C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 12.6. PSW: Program Status Word Name RS[1:0] PARITY Type Reset SFR Address = 0xD0; Bit-Addressable Name Function Carry Flag. This bit is set when the last arithmetic operation resulted in a carry (addition) or a bor- row (subtraction).
  • Page 76: Prefetch Engine

    C8051T620/1/6/7 & C8051T320/1/2/3 13. Prefetch Engine The C8051T620/1/6/7 & C8051T320/1/2/3 family of devices incorporate a 2-byte prefetch engine. Because the access time of the EPROM memory is 40 ns, and the minimum instruction time is roughly 20 ns, the prefetch engine is necessary for full-speed code execution. Instructions are read from EPROM memory two bytes at a time by the prefetch engine and given to the CIP-51 processor core to execute.
  • Page 77: Comparator0 And Comparator1

    C8051T620/1/6/7 & C8051T320/1/2/3 14. Comparator0 and Comparator1 C8051T620/1/6/7 & C8051T320/1/2/3 devices include two on-chip programmable voltage comparators: Comparator0 is shown in Figure 14.1, Comparator1 is shown in Figure 14.2. The two comparators operate identically with the following exceptions: (1) Their input selections differ as described in Section “14.1.
  • Page 78: Figure 14.2. Comparator1 Functional Block Diagram

    C8051T620/1/6/7 & C8051T320/1/2/3 CPT1CN CP1 + Comparator CP1 - Input Mux Crossbar (SYNCHRONIZER) CP1A CPT1MD CP1EN CP1RIF Interrupt CP1FIF Figure 14.2. Comparator1 Functional Block Diagram The Comparator output can be polled in software, used as an interrupt source, and/or routed to a Port pin.
  • Page 79: Figure 14.3. Comparator Hysteresis Plot

    C8051T620/1/6/7 & C8051T320/1/2/3 CPn+ VIN+ CPn- VIN- CIRCUIT CONFIGURATION Positive Hysteresis Voltage (Programmed with CPnHYP Bits) VIN- INPUTS Negative Hysteresis Voltage (Programmed by CPnHYN Bits) VIN+ OUTPUT Negative Hysteresis Maximum Disabled Negative Hysteresis Positive Hysteresis Maximum Disabled Positive Hysteresis Figure 14.3. Comparator Hysteresis Plot The Comparator hysteresis is software-programmable via its Comparator Control register CPTnCN (for n = 0 or 1).
  • Page 80: Sfr Definition 14.1. Cpt0Cn: Comparator0 Control

    C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 14.1. CPT0CN: Comparator0 Control CP0EN CP0OUT CP0RIF CP0FIF CP0HYP[1:0] CP0HYN[1:0] Name Type Reset SFR Address = 0x9B Name Function CP0EN Comparator0 Enable Bit. 0: Comparator0 Disabled. 1: Comparator0 Enabled. CP0OUT Comparator0 Output State Flag. 0: Voltage on CP0+ < CP0–.
  • Page 81: Sfr Definition 14.2. Cpt0Md: Comparator0 Mode Selection

    C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 14.2. CPT0MD: Comparator0 Mode Selection CP0RIE CP0FIE CP0MD[1:0] Name Type Reset SFR Address = 0x9D Name Function Unused Read = 00b, Write = Don’t Care. CP0RIE Comparator0 Rising-Edge Interrupt Enable. 0: Comparator0 Rising-edge interrupt disabled.
  • Page 82: Sfr Definition 14.3. Cpt1Cn: Comparator1 Control

    C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 14.3. CPT1CN: Comparator1 Control CP1EN CP1OUT CP1RIF CP1FIF CP1HYP[1:0] CP1HYN[1:0] Name Type Reset SFR Address = 0x9A Name Function CP1EN Comparator1 Enable Bit. 0: Comparator1 Disabled. 1: Comparator1 Enabled. CP1OUT Comparator1 Output State Flag. 0: Voltage on CP1+ < CP0–.
  • Page 83: Sfr Definition 14.4. Cpt1Md: Comparator1 Mode Selection

    C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 14.4. CPT1MD: Comparator1 Mode Selection CP1RIE CP1FIE CP1MD[1:0] Name Type Reset SFR Address = 0x9C Name Function Unused Read = 00b, Write = Don’t Care. CP1RIE Comparator1 Rising-Edge Interrupt Enable. 0: Comparator1 Rising-edge interrupt disabled.
  • Page 84: Comparator Multiplexers

    C8051T620/1/6/7 & C8051T320/1/2/3 14.1. Comparator Multiplexers C8051T620/1/6/7 & C8051T320/1/2/3 devices include an analog input multiplexer to connect Port I/O pins to the comparator inputs. The Comparator inputs are selected in the CPTnMX registers (SFR Definition 14.5 and SFR Definition 14.6). The CMXnP2–CMXnP0 bits select the Comparator positive input; the CMXnN2–CMXnN0 bits select the Comparator negative input.
  • Page 85: Sfr Definition 14.5. Cpt0Mx: Comparator0 Mux Selection

    C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 14.5. CPT0MX: Comparator0 MUX Selection CMX0N[2:0] CMX0P[2:0] Name Type Reset SFR Address = 0x9F Name Function Unused Read = 0b; Write = don’t care. 6:4 CMX0N[2:0] Comparator0 Negative Input MUX Selection. 000: P1.1 001: P1.5 010: P2.1...
  • Page 86: Sfr Definition 14.6. Cpt1Mx: Comparator1 Mux Selection

    C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 14.6. CPT1MX: Comparator1 MUX Selection CMX1N[2:0] CMX1P[2:0] Name Type Reset SFR Address = 0x9E Name Function Unused Read = 0b; Write = don’t care. 6:4 CMX1N[2:0] Comparator1 Negative Input MUX Selection. 000: P1.3 001: P1.7 010: P2.3...
  • Page 87: Memory Organization

    Program and data memory share the same address space but are accessed via different instruction types. The memory organization of the C8051T620/1/6/7 & C8051T320/1/2/3 device family is shown in Figure 15.1 DATA MEMORY (RAM)
  • Page 88: Program Memory

    Figure 15.2. C8051T626/7 Memory Map 15.1. Program Memory The CIP-51 core has a 64 kB program memory space. The C8051T620/1/6/7 & C8051T320/1/2/3 imple- ments up to 65535 bytes of this program memory space as in-system byte-programmable EPROM. Refer to Table 2.1 on page 21 or Figure 15.1 for additional details on program memory size. Figure 15.3 shows the program memory maps for C8051T620/1/6/7 &...
  • Page 89: Derivative Id

    Section “9.1. Calibration” on page 58. 15.1.3. Serialization All C8051T620/1/6/7 & C8051T320/1/2/3 devices have a factory serialization located in EPROM memory. This value is unique to each device. The serial number is located at the address indicated in Figure 15.3 and can be accessed like any constant array in program memory.
  • Page 90: Data Memory

    C8051T620/1/6/7 & C8051T320/1/2/3 15.2. Data Memory The C8051T620/1 and C8051T320/1/2/3 device family includes 1280 bytes of RAM data memory, while the C8051T626/6 devices include 3328 bytes. 256 bytes of this memory is mapped into the internal RAM space of the 8051. The remaining 1024 or 3072 bytes of this memory is on-chip "external" memory. The data memory map is shown in Figure 15.1 and Figure 15.2 for reference.
  • Page 91: External Ram

    "don't cares" (when USBFAE is cleared to 0). As a result, the XRAM is mapped modulo style over the entire 64 k external data memory address range. For example, on the C8051T620/1 the XRAM byte at address 0x0000 is shadowed at addresses 0x0400, 0x0800, 0x0C00, 0x1000, etc. This is a useful feature when performing a linear memory fill, as the address pointer doesn't have to be reset when reaching the RAM block boundary.
  • Page 92: Figure 15.4. C8051T620/1 And C8051T320/1/2/3 Usb Fifo Space And

    USB FIFO Space 0x0640 (USB Clock Domain) 0x063F Endpoint3 (512 bytes) 0x0440 0x043F Free (64 bytes) 0x0400 0x03FF On-Chip XRAM 0x0000 Figure 15.4. C8051T620/1 and C8051T320/1/2/3 USB FIFO Space and XRAM Memory Map with USBFAE Set to 1 Rev. 1.2...
  • Page 93: Figure 15.5. C8051T626/7 Usb Fifo Space And Xram Memory Map

    C8051T620/1/6/7 & C8051T320/1/2/3 Same 8192 bytes as 0xFFFF 0x0000 to 0x1FFF, wrapped at 8192-byte 0x2000 boundaries 0x1FFF USB FIFO space repeated 3 times 0x1400 0x13FF Endpoint0 (64 bytes) 0x13C0 0x13BF Endpoint1 (128 bytes) 0x1340 0x133F Endpoint2 (256 bytes) USB FIFO Space...
  • Page 94: Sfr Definition 15.2. Emi0Cf: External Memory Configuration

    C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 15.2. EMI0CF: External Memory Configuration USBFAE Name Type Reset SFR Address = 0x85 Name Function Unused Read = 0b; Write = Don’t Care. USBFAE USB FIFO Access Enable. 0: USB FIFO RAM not available through MOVX instructions.
  • Page 95: Special Function Registers

    SFRs used to configure and access the sub-systems unique to the C8051T620/1/6/7 & C8051T320/1/2/3. This allows the addition of new functionality while retaining compatibility with the MCS-51™ instruction set. Table 16.1 lists the SFRs implemented in the C8051T620/1/6/7 &...
  • Page 96: Table 16.2. Special Function Registers

    C8051T620/1/6/7 & C8051T320/1/2/3 Table 16.2. Special Function Registers SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register Address Description Page 0xE0 Accumulator 0xBC ADC0 Configuration ADC0CF 0xE8 ADC0 Control ADC0CN 0xC4 ADC0 Greater-Than Compare High ADC0GTH...
  • Page 97 C8051T620/1/6/7 & C8051T320/1/2/3 Table 16.2. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register Address Description Page 0xF5 In-Application Programming Control IAPCN 0xA8 Interrupt Enable 0xB8 Interrupt Priority 0xE4 INT0/INT1 Configuration IT01CF...
  • Page 98 C8051T620/1/6/7 & C8051T320/1/2/3 Table 16.2. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register Address Description Page 0xFC PCA Capture 0 High PCA0CPH0 0xEA PCA Capture 1 High PCA0CPH1 0xEC PCA Capture 2 High...
  • Page 99 C8051T620/1/6/7 & C8051T320/1/2/3 Table 16.2. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register Address Description Page 0xB4 UART1 Baud Rate Generator Low Byte SBRLL1 0x99 UART0 Data Buffer SBUF0 0xD3 UART1 Data Buffer...
  • Page 100 C8051T620/1/6/7 & C8051T320/1/2/3 Table 16.2. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register Address Description Page 0x95 Timer/Counter 3 High TMR3H 0x94 Timer/Counter 3Low TMR3L 0x93 Timer/Counter 3 Reload High TMR3RLH...
  • Page 101: Interrupts

    C8051T620/1/6/7 & C8051T320/1/2/3 17. Interrupts The C8051T620/1/6/7 & C8051T320/1/2/3 include an extended interrupt system supporting a total of 18 interrupt sources with two priority levels. The allocation of interrupt sources between on-chip peripher- als and external inputs pins varies according to the specific version of the device. Each interrupt source has one or more associated interrupt-pending flag(s) located in an SFR.
  • Page 102: Mcu Interrupt Sources And Vectors

    C8051T620/1/6/7 & C8051T320/1/2/3 17.1. MCU Interrupt Sources and Vectors The C8051T620/1/6/7 & C8051T320/1/2/3 MCUs support 18 interrupt sources. Software can simulate an interrupt by setting any interrupt-pending flag to logic 1. If interrupts are enabled for the flag, an interrupt request will be generated and the CPU will vector to the ISR address associated with the interrupt-pending flag.
  • Page 103: Table 17.1. Interrupt Summary

    C8051T620/1/6/7 & C8051T320/1/2/3 Table 17.1. Interrupt Summary Interrupt Source Interrupt Priority Pending Flag Enable Priority Vector Order Flag Control Reset 0x0000 None N/A N/A Always Always Enabled Highest External Interrupt 0 0x0003 IE0 (TCON.1) EX0 (IE.0) PX0 (IP.0) (INT0) Timer 0 Overflow 0x000B TF0 (TCON.5)
  • Page 104: Sfr Definition 17.1. Ie: Interrupt Enable

    C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 17.1. IE: Interrupt Enable ESPI0 Name Type Reset SFR Address = 0xA8; Bit-Addressable Name Function Enable All Interrupts. Globally enables/disables all interrupts. It overrides individual interrupt mask settings. 0: Disable all interrupt sources. 1: Enable each interrupt according to its individual mask setting.
  • Page 105: Sfr Definition 17.2. Ip: Interrupt Priority

    C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 17.2. IP: Interrupt Priority PSPI0 Name Type Reset SFR Address = 0xB8; Bit-Addressable Name Function Unused Read = 1b, Write = Don't Care. PSPI0 Serial Peripheral Interface (SPI0) Interrupt Priority Control. This bit sets the priority of the SPI0 interrupt.
  • Page 106: Sfr Definition 17.3. Eie1: Extended Interrupt Enable 1

    C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 17.3. EIE1: Extended Interrupt Enable 1 ECP1 ECP0 EPCA0 EADC0 EWADC0 EUSB0 ESMB0 Name Type Reset SFR Address = 0xE6 Name Function Enable Timer 3 Interrupt. This bit sets the masking of the Timer 3 interrupt.
  • Page 107: Sfr Definition 17.4. Eip1: Extended Interrupt Priority 1

    C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 17.4. EIP1: Extended Interrupt Priority 1 PCP1 PCP0 PPCA0 PADC0 PWADC0 PUSB0 PSMB0 Name Type Reset SFR Address = 0xF6 Name Function Timer 3 Interrupt Priority Control. This bit sets the priority of the Timer 3 interrupt.
  • Page 108: Sfr Definition 17.5. Eie2: Extended Interrupt Enable 2

    C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 17.5. EIE2: Extended Interrupt Enable 2 Name Reserved EMAT Reserved EVBUS Type Reset SFR Address = 0xE7 Name Function Unused Read = 0000b, Write = Don't Care. Reserved Must write 0b. EMAT Enable Port Match Interrupts.
  • Page 109: Sfr Definition 17.6. Eip2: Extended Interrupt Priority 2

    C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 17.6. EIP2: Extended Interrupt Priority 2 Name Reserved PMAT Reserved PVBUS Type Reset SFR Address = 0xF7 Name Function Unused Read = 0000b, Write = Don't Care. Reserved Must Write 0b. PMAT Port Match Interrupt Priority Control.
  • Page 110: Int0 And Int1 External Interrupt Sources

    C8051T620/1/6/7 & C8051T320/1/2/3 17.3. INT0 and INT1 External Interrupt Sources The INT0 and INT1 external interrupt sources are configurable as active high or low, edge or level sensi- tive. The IN0PL (INT0 Polarity) and IN1PL (INT1 Polarity) bits in the IT01CF register select active high or active low;...
  • Page 111: Sfr Definition 17.7. It01Cf: Int0/Int1 Configurationo

    C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 17.7. IT01CF: INT0/INT1 Configuration IN1PL IN1SL[2:0] IN0PL IN0SL[2:0] Name Type Reset SFR Address = 0xE4 Name Function IN1PL INT1 Polarity. 0: INT1 input is active low. 1: INT1 input is active high. IN1SL[2:0] INT1 Port Pin Selection Bits.
  • Page 112: Program Memory (Eprom)

    C8051T620/1/6/7 & C8051T320/1/2/3 18. Program Memory (EPROM) C8051T620/1/6/7 & C8051T320/1/2/3 devices include 64, 32, or 16 kB of on-chip byte-programmable EPROM for program code storage. The EPROM memory can be programmed via the C2 debug and pro- gramming interface when a special programming voltage is applied to the V pin.
  • Page 113: Eprom In-Application Programming

    C8051T620/1/6/7 & C8051T320/1/2/3 18.1.2. EPROM In-Application Programming The EPROM of the C8051T620/1/6/7 & C8051T320/1/2/3 devices has an In-Application Programming option. In-Application Programming will be much slower than normal programming where the V pro- gramming voltage is applied to the V pin, but it allows a small number of bytes to be programmed any- where in the non-reserved areas of the EPROM.
  • Page 114: Security Options

    C2 interface. On the C8051T626/7 devices, the security byte is located at address 0xFFF8. On the C8051T620/1 and C8051T320/1/2/3, the security byte is located at address 0x3FF8. The lock byte can always be read regardless of the security settings.
  • Page 115: Pswe Maintenance

    C8051T620/1/6/7 & C8051T320/1/2/3 6. Make certain that all writes to the RSTSRC register explicitly set the PORSF bit to a 1. Areas to check are initialization code which enables other reset sources, such as the Missing Clock Detector, for example, and instructions which force a Software Reset. A global search on "RSTSRC" can quickly verify this.
  • Page 116: Sfr Definition 18.1. Psctl: Program Store R/W Control

    C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 18.1. PSCTL: Program Store R/W Control PSWE Name Type Reset SFR Address = 0x8F Name Function Unused Read = 0000000b. Write = don’t care. PSWE Program Store Write Enable. Setting this bit allows writing a byte of data to the EPROM program memory using the MOVX write instruction.
  • Page 117: Sfr Definition 18.3. Iapcn: In-Application Programming Control

    C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 18.3. IAPCN: In-Application Programming Control IAPEN IAPDISD Name Type Reset SFR Address = 0xF5 Name Function IAPEN In-Application Programming Enable. 0: In-Application Programming is disabled. 1: In-Application Programming is enabled. IAPHWD In-Application Programming Hardware Disable.
  • Page 118: Power Management Modes

    SFR Definition 19.1 describes the Power Control Register (PCON) used to control the C8051T620/1/6/7 & C8051T320/1/2/3's Stop and Idle power management modes. Suspend mode is controlled by the SUSPEND bit in the OSCICN register (SFR Definition 21.3).
  • Page 119: Stop Mode

    C8051T620/1/6/7 & C8051T320/1/2/3 vides the opportunity for additional power savings, allowing the system to remain in the Idle mode indefi- nitely, waiting for an external stimulus to wake up the system. Refer to Section “20.6. PCA Watchdog Timer Reset” on page 125 for more information on the use and configuration of the WDT.
  • Page 120: Sfr Definition 19.1. Pcon: Power Control

    C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 19.1. PCON: Power Control GF[5:0] STOP IDLE Name Type Reset SFR Address = 0x87 Name Function GF[5:0] General Purpose Flags 5–0. These are general purpose flags for use under software control. STOP Stop Mode Select.
  • Page 121: Reset Sources

    C8051T620/1/6/7 & C8051T320/1/2/3 20. Reset Sources Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset state, the following occur:  CIP-51 halts program execution  Special Function Registers (SFRs) are initialized to their defined reset values ...
  • Page 122: Power-On Reset

    C8051T620/1/6/7 & C8051T320/1/2/3 20.1. Power-On Reset During power-up, the device is held in a reset state and the RST pin is driven low until V settles above . A delay occurs before the device is released from reset; the delay decreases as the V...
  • Page 123 C8051T620/1/6/7 & C8051T320/1/2/3 the level required for data retention. If the PORSF flag reads 1, the data may no longer be valid. The V monitor is enabled after power-on resets. Its defined state (enabled/disabled) is not altered by any other reset source.
  • Page 124: External Reset

    C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 20.1. VDM0CN: V Monitor Control VDMEN VDDSTAT Name Type Varies Varies Varies Varies Varies Varies Varies Varies Reset SFR Address = 0xFF Name Function VDMEN Monitor Enable. This bit turns the V monitor circuit on/off. The V...
  • Page 125: Pca Watchdog Timer Reset

    C8051T620/1/6/7 & C8051T320/1/2/3 20.6. PCA Watchdog Timer Reset The programmable Watchdog Timer (WDT) function of the Programmable Counter Array (PCA) can be used to prevent software from running out of control during a system malfunction. The PCA WDT function can be enabled or disabled by software as described in Section “29.4. Watchdog Timer Mode” on page 279;...
  • Page 126: Sfr Definition 20.2. Rstsrc: Reset Source

    C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 20.2. RSTSRC: Reset Source USBRSF MEMERR C0RSEF SWRSF WDTRSF MCDRSF PORSF PINRSF Name Type Varies Varies Varies Varies Varies Varies Varies Varies Reset SFR Address = 0xEF Name Description Write Read USBRSF USB Reset Flag...
  • Page 127: Oscillators And Clock Selection

    C8051T620/1/6/7 & C8051T320/1/2/3 21. Oscillators and Clock Selection C8051T620/1/6/7 & C8051T320/1/2/3 devices include a programmable internal high-frequency oscillator, a programmable internal low-frequency oscillator, and an external oscillator drive circuit. The internal high- frequency oscillator can be enabled/disabled and calibrated using the OSCICN and OSCICL registers, as shown in Figure 21.1.
  • Page 128: System Clock Selection

    C8051T620/1/6/7 & C8051T320/1/2/3 21.1. System Clock Selection The CLKSL[2:0] bits in register CLKSEL select which oscillator source is used as the system clock. CLKSL[2:0] must be set to 001b for the system clock to run from the external oscillator; however the exter- nal oscillator may still clock certain peripherals (timers, PCA) when the internal oscillator is selected as the system clock.
  • Page 129: Sfr Definition 21.1. Clksel: Clock Select

    C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 21.1. CLKSEL: Clock Select USBCLK[2:0] OUTCLK CLKSL[2:0] Name Type Reset SFR Address = 0xA9 Name Function Unused Read = 0b; Write = Don’t Care 6:4 USBCLK[2:0] USB Clock Source Select Bits. 000: USBCLK derived from the Internal High-Frequency Oscillator.
  • Page 130: Programmable Internal High-Frequency (H-F) Oscillator

    OSCICL register as defined by SFR Definition 21.2. On C8051T620/1/6/7 & C8051T320/1/2/3 devices, OSCICL is factory calibrated to obtain a 48 MHz base frequency. Note that the system clock may be derived from the programmed internal oscillator divided by 1, 2, 4, or 8 after a divide by 4 stage, as defined by the IFCN bits in register OSCICN.
  • Page 131: Sfr Definition 21.3. Oscicn: Internal H-F Oscillator Control

    C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 21.3. OSCICN: Internal H-F Oscillator Control IOSCEN IFRDY SUSPEND IFCN[1:0] Name Type Reset SFR Address = 0xB2 Name Function IOSCEN Internal H-F Oscillator Enable Bit. 0: Internal H-F Oscillator Disabled. 1: Internal H-F Oscillator Enabled.
  • Page 132: Clock Multiplier

    C8051T620/1/6/7 & C8051T320/1/2/3 21.4. Clock Multiplier The C8051T620/1/6/7 & C8051T320/1/2/3 device includes a 48 MHz high-frequency oscillator instead of a 12 MHz oscillator and a 4x Clock Multiplier, so the USB0 module can be run directly from the internal high- frequency oscillator.
  • Page 133: Programmable Internal Low-Frequency (L-F) Oscillator

    C8051T620/1/6/7 & C8051T320/1/2/3 21.5. Programmable Internal Low-Frequency (L-F) Oscillator All C8051T620/1/6/7 & C8051T320/1/2/3 devices include a programmable low-frequency internal oscilla- tor, which is calibrated to a nominal frequency of 80 kHz. The low-frequency oscillator circuit includes a divider that can be changed to divide the clock by 1, 2, 4, or 8, using the OSCLD bits in the OSCLCN reg- ister (see SFR Definition 21.5).
  • Page 134: External Oscillator Drive Circuit

    C8051T620/1/6/7 & C8051T320/1/2/3 21.6. External Oscillator Drive Circuit The external oscillator circuit may drive an external crystal, ceramic resonator, capacitor, or RC network. A CMOS clock may also provide a clock input. Figure 21.1 shows a block diagram of the four external oscil- lator options.
  • Page 135: Figure 21.2. External Crystal Example

    C8051T620/1/6/7 & C8051T320/1/2/3 13 pF XTAL1 10 M 32 kHz XTAL2 13 pF Figure 21.2. External Crystal Example Important Note on External Crystals: Crystal oscillator circuits are quite sensitive to PCB layout. The crystal should be placed as close as possible to the XTAL pins on the device. The traces should be as short as possible and shielded with ground plane from any other traces which could introduce noise or interference.
  • Page 136: External Rc Example

    C8051T620/1/6/7 & C8051T320/1/2/3 21.6.2. External RC Example If an RC network is used as an external oscillator source for the MCU, the circuit should be configured as shown in Figure 21.1, “RC Mode”. The capacitor should be no greater than 100 pF; however, for very small capacitors, the total capacitance may be dominated by parasitic capacitance in the PCB layout.
  • Page 137: Sfr Definition 21.6. Oscxcn: External Oscillator Control

    C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 21.6. OSCXCN: External Oscillator Control Name XCLKVLD XOSCMD[2:0] XFCN[2:0] Type Reset SFR Address = 0xB1 Name Function XCLKVLD External Oscillator Valid Flag. Provides External Oscillator status and is valid at all times for all modes of opera- tion except External CMOS Clock Mode and External CMOS Clock Mode with divide by 2.
  • Page 138: Port Input/Output

    C8051T620/1/6/7 & C8051T320/1/2/3 22. Port Input/Output Digital and analog resources are available through 21, 24, or 25 I/O pins, depending on the specific device. Port pins P0.0-P2.7 can be defined as general-purpose I/O (GPIO), assigned to one of the internal digital resources, or assigned to an analog function as shown in Figure 22.3.
  • Page 139: Port I/O Modes Of Operation

    C8051T620/1/6/7 & C8051T320/1/2/3 22.1. Port I/O Modes of Operation Port pins use the Port I/O cell shown in Figure 22.2. Each Port I/O cell can be configured by software for analog I/O or digital I/O using the PnMDIN registers. On reset, all Port I/O cells default to a high impedance state with weak pull-ups enabled until the Crossbar is enabled (XBARE = 1).
  • Page 140: Interfacing Port I/O To 5 V Logic

    C8051T620/1/6/7 & C8051T320/1/2/3 22.1.3. Interfacing Port I/O to 5 V Logic All Port I/O configured for digital, open-drain operation are capable of interfacing to digital logic operating at a supply voltage higher than V and less than 5.25V. An external pull-up resistor to the higher supply volt- age is typically required for most systems.
  • Page 141: Assigning Port I/O Pins To External Digital Event Capture Functions

    C8051T620/1/6/7 & C8051T320/1/2/3 Table 22.2. Port I/O Assignment for Digital Functions Digital Function Potentially Assignable Port Pins Suffers) used for Assignment UART0, SPI0, SMBus, CP0, Any Port pin available for assignment by the XBR0, XBR1, XBR2 CP0A, CP1, CP1A, Crossbar. This includes P0.0 - P2.6 pins which SYSCLK, PCA0 (CEX0-4 have their PnSKIP bit set to 0.
  • Page 142: Priority Crossbar Decoder

    C8051T620/1/6/7 & C8051T320/1/2/3 Table 22.3. Port I/O Assignment for External Digital Event Capture Functions Digital Function Potentially Assignable Port Pins SFR(s) used for Assignment External Interrupt 0 P0.0 - P0.7 IT01CF External Interrupt 1 P0.0 - P0.7 IT01CF Port Match P0.0 - P1.7...
  • Page 143: Figure 22.3. Priority Crossbar Decoder Potential Pin Assignments

    C8051T620/1/6/7 & C8051T320/1/2/3 Port Pin Number 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 Special Function Signals MISO MOSI CP0A CP1A SYSCLK CEX0 CEX1...
  • Page 144: Figure 22.4. Priority Crossbar Decoder Example 1-No Skipped Pins

    C8051T620/1/6/7 & C8051T320/1/2/3 Port Pin Number 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 Special Function Signals MISO MOSI CP0A CP1A SYSCLK CEX0 CEX1...
  • Page 145: Figure 22.5. Priority Crossbar Decoder Example 2-Skipping Pins

    C8051T620/1/6/7 & C8051T320/1/2/3 Port Pin Number 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 Special Function Signals MISO MOSI CP0A CP1A SYSCLK CEX0 CEX1 CEX2 CEX3...
  • Page 146: Port I/O Initialization

    C8051T620/1/6/7 & C8051T320/1/2/3 22.4. Port I/O Initialization Port I/O initialization consists of the following steps: 1. Select the input mode (analog or digital) for all Port pins, using the Port Input Mode register (PnMDIN). 2. Select the output mode (open-drain or push-pull) for all Port pins, using the Port Output Mode register (PnMDOUT).
  • Page 147: Sfr Definition 22.1. Xbr0: Port I/O Crossbar Register 0

    C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 22.1. XBR0: Port I/O Crossbar Register 0 Name CP1AE CP1E CP0AE CP0E SYSCKE SMB0E SPI0E URT0E Type Reset SFR Address = 0xE1 Name Function CP1AE Comparator1 Asynchronous Output Enable. 0: Asynchronous CP1 unavailable at Port pin.
  • Page 148: Sfr Definition 22.2. Xbr1: Port I/O Crossbar Register 1

    C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 22.2. XBR1: Port I/O Crossbar Register 1 Name WEAKPUD XBARE ECIE PCA0ME[2:0] Type Reset SFR Address = 0xE2 Name Function WEAKPUD Port I/O Weak Pullup Disable. 0: Weak Pullups enabled (except for Ports whose I/O are configured for analog mode).
  • Page 149: Port Match

    C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 22.3. XBR2: Port I/O Crossbar Register 2 Name Reserved URT1E Type Reset SFR Address = 0xE3 Name Function Unused Read = 0000000b; Write = Don’t Care. Reserved Must write 0. URT1E UART1 I/O Output Enable Bit.
  • Page 150: Sfr Definition 22.4. P0Mask: Port 0 Mask Register

    C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 22.4. P0MASK: Port 0 Mask Register Name P0MASK[7:0] Type Reset SFR Address = 0xAE Name Function P0MASK[7:0] Port 0 Mask Value. Selects P0 pins to be compared to the corresponding bits in P0MAT. 0: P0.n pin logic value is ignored and cannot cause a Port Mismatch event.
  • Page 151: Sfr Definition 22.6. P1Mask: Port 1 Mask Register

    C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 22.6. P1MASK: Port 1 Mask Register Name P1MASK[7:0] Type Reset SFR Address = 0xBA Name Function P1MASK[7:0] Port 1 Mask Value. Selects P1 pins to be compared to the corresponding bits in P1MAT. 0: P1.n pin logic value is ignored and cannot cause a Port Mismatch event.
  • Page 152: Special Function Registers For Accessing And Configuring Port I/O

    C8051T620/1/6/7 & C8051T320/1/2/3 22.6. Special Function Registers for Accessing and Configuring Port I/O All Port I/O are accessed through corresponding special function registers (SFRs) that are both byte addressable and bit addressable. When writing to a Port, the value written to the SFR is latched to main- tain the output data value at each pin.
  • Page 153: Sfr Definition 22.9. P0Mdin: Port 0 Input Mode

    C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 22.9. P0MDIN: Port 0 Input Mode Name P0MDIN[7:0] Type Reset SFR Address = 0xF1 Name Function P0MDIN[7:0] Analog Configuration Bits for P0.7–P0.0 (respectively). Port pins configured for analog mode have their weak pullup, digital driver, and digital receiver disabled.
  • Page 154: Sfr Definition 22.11. P0Skip: Port 0 Skip

    C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 22.11. P0SKIP: Port 0 Skip Name P0SKIP[7:0] Type Reset SFR Address = 0xD4 Name Function P0SKIP[7:0] Port 0 Crossbar Skip Enable Bits. These bits select Port 0 pins to be skipped by the Crossbar Decoder. Port pins used for analog, special functions or GPIO should be skipped by the Crossbar.
  • Page 155: Sfr Definition 22.13. P1Mdin: Port 1 Input Mode

    C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 22.13. P1MDIN: Port 1 Input Mode Name P1MDIN[7:0] Type Reset SFR Address = 0xF2 Name Function P1MDIN[7:0] Analog Configuration Bits for P1.7–P1.0 (respectively). Port pins configured for analog mode have their weak pullup, digital driver, and digital receiver disabled.
  • Page 156: Sfr Definition 22.15. P1Skip: Port 1 Skip

    C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 22.15. P1SKIP: Port 1 Skip Name P1SKIP[7:0] Type Reset SFR Address = 0xD5 Name Function P1SKIP[7:0] Port 1 Crossbar Skip Enable Bits. These bits select Port 1 pins to be skipped by the Crossbar Decoder. Port pins used for analog, special functions or GPIO should be skipped by the Crossbar.
  • Page 157: Sfr Definition 22.17. P2Mdin: Port 2 Input Mode

    C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 22.17. P2MDIN: Port 2 Input Mode Name P2MDIN[7:0] Type Reset SFR Address = 0xF3 Name Function P2MDIN[7:0] Analog Configuration Bits for P2.7–P2.0 (respectively). Port pins configured for analog mode have their weak pullup, digital driver, and digital receiver disabled.
  • Page 158: Sfr Definition 22.19. P2Skip: Port 2 Skip

    C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 22.19. P2SKIP: Port 2 Skip Name P2SKIP[7:0] Type Reset SFR Address = 0xD6 Name Function P2SKIP[7:0] Port 2 Crossbar Skip Enable Bits. These bits select Port 2 pins to be skipped by the Crossbar Decoder. Port pins used for analog, special functions or GPIO should be skipped by the Crossbar.
  • Page 159: Sfr Definition 22.21. P3Mdout: Port 3 Output Mode

    C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 22.21. P3MDOUT: Port 3 Output Mode Name P3MDOUT[0] Type Reset SFR Address = 0xA7 Name Function Unused Read = 0000000b; Write = Don’t Care P3MDOUT[0] Output Configuration Bits for P3.0. 0: P3.0 Output is open-drain.
  • Page 160: Universal Serial Bus Controller (Usb0)

    C8051T620/1/6/7 & C8051T320/1/2/3 23. Universal Serial Bus Controller (USB0) C8051T620/1/6/7 & C8051T320/1/2/3 devices include a complete Full/Low Speed USB function for USB peripheral implementations. The USB Function Controller (USB0) consists of a Serial Interface Engine (SIE), USB Transceiver (including matching resistors and configurable pull-up resistors), 1 kB FIFO block, and clock recovery mechanism for crystal-less operation.
  • Page 161: Endpoint Addressing

    C8051T620/1/6/7 & C8051T320/1/2/3 23.1. Endpoint Addressing A total of eight endpoint pipes are available. The control endpoint (Endpoint0) always functions as a bi- directional IN/OUT endpoint. The other endpoints are implemented as three pairs of IN/OUT endpoint pipes: Table 23.1. Endpoint Addressing Scheme...
  • Page 162: Sfr Definition 23.1. Usb0Xcn: Usb0 Transceiver Control

    C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 23.1. USB0XCN: USB0 Transceiver Control PREN PHYEN SPEED PHYTST[1:0] DFREC Name Type Reset SFR Address = 0xD7 Name Function PREN Internal Pull-up Resistor Enable. The location of the pull-up resistor (D+ or D-) is determined by the SPEED bit.
  • Page 163: Usb Register Access

    C8051T620/1/6/7 & C8051T320/1/2/3 23.3. USB Register Access The USB0 controller registers listed in Table 23.2 are accessed through two SFRs: USB0 Address (USB0ADR) and USB0 Data (USB0DAT). The USB0ADR register selects which USB register is targeted by reads/writes of the USB0DAT register. See Figure 23.2.
  • Page 164: Sfr Definition 23.2. Usb0Adr: Usb0 Indirect Address

    C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 23.2. USB0ADR: USB0 Indirect Address BUSY AUTORD USBADDR[5:0] Name Type Reset SFR Address = 0x96 Name Description Write Read BUSY 0: No effect. 0: USB0DAT register data USB0 Register Read 1: A USB0 indirect regis- is valid.
  • Page 165: Sfr Definition 23.3. Usb0Dat: Usb0 Data

    C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 23.3. USB0DAT: USB0 Data USB0DAT[7:0] Name Type Reset SFR Address = 0x97 Name Description Write Read USB0DAT[7:0] USB0 Data Bits. Write Procedure: Read Procedure: 1. Poll for BUSY 1. Poll for BUSY This SFR is used to indi- (USB0ADR.7) =>...
  • Page 166: Table 23.2. Usb0 Controller Registers

    C8051T620/1/6/7 & C8051T320/1/2/3 Table 23.2. USB0 Controller Registers USB Register USB Register Description Page Number Name Address Interrupt Registers IN1INT 0x02 Endpoint0 and Endpoints1-3 IN Interrupt Flags OUT1INT 0x04 Endpoints1-3 OUT Interrupt Flags CMINT 0x06 Common USB Interrupt Flags IN1IE...
  • Page 167 C8051T620/1/6/7 & C8051T320/1/2/3 USB Register Definition 23.4. INDEX: USB0 Endpoint Index Name EPSEL[3:0] Type Reset USB Register Address = 0x0E Name Function Unused Read = 0000b. Write = don’t care. EPSEL[3:0] Endpoint Select Bits. These bits select which endpoint is targeted when indexed USB0 registers are accessed.
  • Page 168: Usb Clock Configuration

    C8051T620/1/6/7 & C8051T320/1/2/3 23.4. USB Clock Configuration USB0 is capable of communication as a Full or Low Speed USB function. Communication speed is selected via the SPEED bit in SFR USB0XCN. When operating as a Low Speed function, the USB0 clock must be 6 MHz.
  • Page 169: Fifo Management

    IN, OUT, or both (Split (256 bytes) Mode) 0x0640 0x063F Endpoint3 (512 bytes) 0x0440 0x043F Free (64 bytes) 0x0400 USB Clock Domain System Clock Domain 0x03FF User XRAM (1024 bytes) 0x0000 Figure 23.3. C8051T620/1 and C8051T320/1/2/3 USB FIFO Allocation Rev. 1.2...
  • Page 170: Fifo Split Mode

    C8051T620/1/6/7 & C8051T320/1/2/3 0x13FF Endpoint0 (64 bytes) 0x13C0 0x13BF Endpoint1 (128 bytes) 0x1340 0x133F Configurable as Endpoint2 IN, OUT, or both (Split (256 bytes) Mode) 0x1240 0x123F Endpoint3 (512 bytes) 0x1040 0x103F Free (64 bytes) 0x1000 USB Clock Domain System Clock Domain...
  • Page 171: Fifo Access

    C8051T620/1/6/7 & C8051T320/1/2/3 Table 23.3. FIFO Configurations Endpoint Split Mode Maximum IN Packet Size Maximum OUT Packet Size Number Enabled? (Double Buffer Disabled / (Double Buffer Disabled / Enabled) Enabled) 128 / 64 64 / 32 64 / 32 256 / 128...
  • Page 172: Function Addressing

    C8051T620/1/6/7 & C8051T320/1/2/3 23.6. Function Addressing The FADDR register holds the current USB0 function address. Software should write the host-assigned 7- bit function address to the FADDR register when received as part of a SET_ADDRESS command. A new address written to FADDR will not take effect (USB0 will not respond to the new address) until the end of the current transfer (typically following the status phase of the SET_ADDRESS command transfer).
  • Page 173: Function Configuration And Control

    C8051T620/1/6/7 & C8051T320/1/2/3 23.7. Function Configuration and Control The USB register POWER (USB Register Definition 23.8) is used to configure and control USB0 at the device level (enable/disable, Reset/Suspend/Resume handling, etc.). USB Reset: The USBRST bit (POWER.3) is set to 1 by hardware when Reset signaling is detected on the bus.
  • Page 174 C8051T620/1/6/7 & C8051T320/1/2/3 USB Register Definition 23.8. POWER: USB0 Power ISOUD USBINH USBRST RESUME SUSMD SUSEN Name Type Reset USB Register Address = 0x01 Name Function ISOUD ISO Update Bit. This bit affects all IN Isochronous endpoints. 0: When software writes INPRDY = 1, USB0 will send the packet when the next IN token is received.
  • Page 175 C8051T620/1/6/7 & C8051T320/1/2/3 USB Register Definition 23.9. FRAMEL: USB0 Frame Number Low FRMEL[7:0] Name Type Reset USB Register Address = 0x0C Name Function 7:0 FRMEL[7:0] Frame Number Low Bits. This register contains bits 7-0 of the last received frame number.
  • Page 176: Interrupts

    C8051T620/1/6/7 & C8051T320/1/2/3 23.8. Interrupts The read-only USB0 interrupt flags are located in the USB registers shown in USB Register Definition 23.11 through USB Register Definition 23.13. The associated interrupt enable bits are located in the USB registers shown in USB Register Definition 23.14 through USB Register Definition 23.16. A USB0 interrupt is generated when any of the USB interrupt flags is set to 1.
  • Page 177 C8051T620/1/6/7 & C8051T320/1/2/3 USB Register Definition 23.12. OUT1INT: USB0 OUT Endpoint Interrupt OUT3 OUT2 OUT1 Name Type Reset USB Register Address = 0x04 Name Function Unused Read = 0000b. Write = don’t care. OUT3 OUT Endpoint 3 Interrupt-pending Flag. This bit is cleared when software reads the OUT1INT register.
  • Page 178 C8051T620/1/6/7 & C8051T320/1/2/3 USB Register Definition 23.13. CMINT: USB0 Common Interrupt RSTINT RSUINT SUSINT Name Type Reset USB Register Address = 0x06 Name Function Unused Read = 0000b. Write = don’t care. Start of Frame Interrupt Flag. Set by hardware when a SOF token is received. This interrupt event is synthesized by hardware: an interrupt will be generated when hardware expects to receive a SOF event, even if the actual SOF signal is missed or corrupted.
  • Page 179 C8051T620/1/6/7 & C8051T320/1/2/3 USB Register Definition 23.14. IN1IE: USB0 IN Endpoint Interrupt Enable IN3E IN2E IN1E EP0E Name Type Reset USB Register Address = 0x07 Name Function Unused Read = 0000b. Write = don’t care. IN3E IN Endpoint 3 Interrupt Enable.
  • Page 180 C8051T620/1/6/7 & C8051T320/1/2/3 USB Register Definition 23.15. OUT1IE: USB0 OUT Endpoint Interrupt Enable OUT3E OUT2E OUT1E Name Type Reset USB Register Address = 0x09 Name Function Unused Read = 0000b. Write = don’t care. OUT3E OUT Endpoint 3 Interrupt Enable.
  • Page 181: The Serial Interface Engine

    C8051T620/1/6/7 & C8051T320/1/2/3 USB Register Definition 23.16. CMIE: USB0 Common Interrupt Enable SOFE RSTINTE RSUINTE SUSINTE Name Type Reset USB Register Address = 0x0B Name Function Unused Read = 0000b. Write = don’t care. SOFE Start of Frame Interrupt Enable.
  • Page 182: Endpoint0 Setup Transactions

    C8051T620/1/6/7 & C8051T320/1/2/3 5. Hardware sets the SUEND bit (E0CSR.4) because a control transfer ended before firmware sets the DATAEND bit (E0CSR.3). The E0CNT register (USB Register Definition 23.11) holds the number of received data bytes in the Endpoint0 FIFO.
  • Page 183: Endpoint0 Out Transactions

    C8051T620/1/6/7 & C8051T320/1/2/3 23.10.3. Endpoint0 OUT Transactions When a SETUP request is received that requires the host to transmit data to USB0, one or more OUT requests will be sent by the host. When an OUT packet is successfully received by USB0, hardware will set the OPRDY bit (E0CSR.0) to 1 and generate an Endpoint0 interrupt.
  • Page 184 C8051T620/1/6/7 & C8051T320/1/2/3 USB Register Definition 23.17. E0CSR: USB0 Endpoint0 Control SSUEND SOPRDY SDSTL SUEND DATAEND STSTL INPRDY OPRDY Name Type Reset USB Register Address = 0x11 Name Description Write Read SSUEND Serviced Setup End Software should set this bit to 1 This bit always reads 0.
  • Page 185: Configuring Endpoints1-3

    C8051T620/1/6/7 & C8051T320/1/2/3 USB Register Definition 23.18. E0CNT: USB0 Endpoint0 Data Count E0CNT[6:0] Name Type Reset USB Register Address = 0x16 Name Function Unused Read = 0b. Write = don’t care. 6:0 E0CNT[6:0] Endpoint 0 Data Count. This 7-bit number indicates the number of received data bytes in the Endpoint 0 FIFO.
  • Page 186: Controlling Endpoints1-3 In

    C8051T620/1/6/7 & C8051T320/1/2/3 USB Register Definition 23.19. EENABLE: USB0 Endpoint Enable EEN3 EEN2 EEN1 Reserved Name Type Reset USB Register Address = 0x1E Name Function Unused Read = 1111b. Write = don’t care. EEN3 Endpoint 3 Enable. This bit enables/disables Endpoint 3.
  • Page 187: Endpoints1-3 In Isochronous Mode

    C8051T620/1/6/7 & C8051T320/1/2/3 ates a STALL condition, an interrupt will be generated and the STSTL bit (EINCSRL.5) set to 1. The STSTL bit must be reset to 0 by firmware. Hardware will automatically reset INPRDY to 0 when a packet slot is open in the endpoint FIFO. Note that if double buffering is enabled for the target endpoint, it is possible for firmware to load two packets into the IN FIFO at a time.
  • Page 188 C8051T620/1/6/7 & C8051T320/1/2/3 USB Register Definition 23.20. EINCSRL: USB0 IN Endpoint Control Low CLRDT STSTL SDSTL FLUSH UNDRUN FIFONE INPRDY Name Type Reset USB Register Address = 0x11 Name Description Write Read Unused Read = 0b. Write = don’t care.
  • Page 189: Controlling Endpoints1-3 Out

    C8051T620/1/6/7 & C8051T320/1/2/3 USB Register Definition 23.21. EINCSRH: USB0 IN Endpoint Control High DBIEN DIRSEL FCDT SPLIT Name Type Reset USB Register Address = 0x12 Name Function DBIEN IN Endpoint Double-buffer Enable. 0: Double-buffering disabled for the selected IN endpoint.
  • Page 190: Endpoints1-3 Out Interrupt Or Bulk Mode

    C8051T620/1/6/7 & C8051T320/1/2/3 23.13.1. Endpoints1-3 OUT Interrupt or Bulk Mode When the ISO bit (EOUTCSRH.6) = 0 the target endpoint operates in Bulk or Interrupt mode. Once an end- point has been configured to operate in Bulk/Interrupt OUT mode (typically following an Endpoint0 SET_INTERFACE command), hardware will set the OPRDY bit (EOUTCSRL.0) to 1 and generate an...
  • Page 191 C8051T620/1/6/7 & C8051T320/1/2/3 USB Register Definition 23.22. EOUTCSRL: USB0 OUT Endpoint Control Low Byte CLRDT STSTL SDSTL FLUSH DATERR OVRUN FIFOFUL OPRDY Name Type Reset USB Register Address = 0x14 Name Description Write Read CLRDT Clear Data Toggle Bit. Software should write 1 to This bit always reads 0.
  • Page 192 C8051T620/1/6/7 & C8051T320/1/2/3 USB Register Definition 23.23. EOUTCSRH: USB0 OUT Endpoint Control High Byte DBOEN Name Type Reset USB Register Address = 0x15 Name Function DBOEN Double-buffer Enable. 0: Double-buffering disabled for the selected OUT endpoint. 1: Double-buffering enabled for the selected OUT endpoint.
  • Page 193 C8051T620/1/6/7 & C8051T320/1/2/3 USB Register Definition 23.25. EOUTCNTH: USB0 OUT Endpoint Count High EOCH[1:0] Name Type Reset USB Register Address = 0x17 Name Function Unused Read = 000000b. Write = don’t care. 1:0 EOCH[1:0] OUT Endpoint Count High Byte. EOCH holds the upper 2-bits of the 10-bit number of data bytes in the last received packet in the current OUT endpoint FIFO.
  • Page 194: Smbus

    C8051T620/1/6/7 & C8051T320/1/2/3 24. SMBus The SMBus I/O interface is a two-wire, bi-directional serial bus. The SMBus is compliant with the System Management Bus Specification, version 1.1, and compatible with the I C serial bus. Reads and writes to the interface by the system controller are byte oriented with the SMBus interface autonomously controlling the serial transfer of the data.
  • Page 195: Supporting Documents

    C8051T620/1/6/7 & C8051T320/1/2/3 24.1. Supporting Documents It is assumed the reader is familiar with or has access to the following supporting documents: 1. The I C-Bus and How to Use It (including specifications), Philips Semiconductor. 2. The I C-Bus Specification—Version 2.0, Philips Semiconductor.
  • Page 196: Transmitter Vs. Receiver

    C8051T620/1/6/7 & C8051T320/1/2/3 All transactions are initiated by a master, with one or more addressed slave devices as the target. The master generates the START condition and then transmits the slave address and direction bit. If the trans- action is a WRITE operation from the master to the slave, the master transmits the data a byte at a time waiting for an ACK from the slave at the end of each byte.
  • Page 197: Scl High (Smbus Free) Timeout

    C8051T620/1/6/7 & C8051T320/1/2/3 overflow after 25 ms (and SMBTOE set), the Timer 3 interrupt service routine can be used to reset (disable and re-enable) the SMBus in the event of an SCL low timeout. 24.3.5. SCL High (SMBus Free) Timeout The SMBus specification stipulates that if the SCL and SDA lines remain high for more that 50 µs, the bus...
  • Page 198: Figure 24.4. Typical Smbus Scl Generation

    C8051T620/1/6/7 & C8051T320/1/2/3 Table 24.1. SMBus Clock Source Selection SMBCS1 SMBCS0 SMBus Clock Source Timer 0 Overflow Timer 1 Overflow Timer 2 High Byte Overflow Timer 2 Low Byte Overflow The SMBCS1–0 bits select the SMBus clock source, which is used only when operating as a master or when the Free Timeout detection is enabled.
  • Page 199 C8051T620/1/6/7 & C8051T320/1/2/3 Setting the EXTHOLD bit extends the minimum setup and hold times for the SDA line. The minimum SDA setup time defines the absolute minimum time that SDA is stable before SCL transitions from low-to-high. The minimum SDA hold time defines the absolute minimum time that the current SDA value remains stable after SCL transitions from high-to-low.
  • Page 200: Sfr Definition 24.1. Smb0Cf: Smbus Clock/Configuration

    C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 24.1. SMB0CF: SMBus Clock/Configuration ENSMB BUSY EXTHOLD SMBTOE SMBFTE SMBCS[1:0] Name Type Reset SFR Address = 0xC1 Name Function ENSMB SMBus Enable. This bit enables the SMBus interface when set to 1. When enabled, the interface constantly monitors the SDA and SCL pins.
  • Page 201: Smb0Cn Control Register

    C8051T620/1/6/7 & C8051T320/1/2/3 24.4.2. SMB0CN Control Register SMB0CN is used to control the interface and to provide status information (see SFR Definition 24.2). The higher four bits of SMB0CN (MASTER, TXMODE, STA, and STO) form a status vector that can be used to jump to service routines.
  • Page 202: Sfr Definition 24.2. Smb0Cn: Smbus Control

    C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 24.2. SMB0CN: SMBus Control MASTER TXMODE ACKRQ ARBLOST Name Type Reset SFR Address = 0xC0; Bit-Addressable Name Description Read Write MASTER SMBus Master/Slave 0: SMBus operating in slave mode. Indicator. This read-only bit 1: SMBus operating in indicates when the SMBus is master mode.
  • Page 203: Hardware Slave Address Recognition

    C8051T620/1/6/7 & C8051T320/1/2/3 Table 24.3. Sources for Hardware Changes to SMB0CN Set by Hardware When: Cleared by Hardware When:  A START is generated.  A STOP is generated. MASTER  Arbitration is lost.  START is generated.  A START is detected.
  • Page 204: Sfr Definition 24.3. Smb0Adr: Smbus Slave Address

    C8051T620/1/6/7 & C8051T320/1/2/3 In this case, either a 1 or a 0 value are acceptable on the incoming slave address. Additionally, if the GC bit in register SMB0ADR is set to 1, hardware will recognize the General Call Address (0x00). Table 24.4 shows some example parameter settings and the slave addresses that will be recognized by hardware under those conditions.
  • Page 205: Sfr Definition 24.4. Smb0Adm: Smbus Slave Address Mask

    C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 24.4. SMB0ADM: SMBus Slave Address Mask SLVM[6:0] EHACK Name Type Reset SFR Address = 0xCF Name Function SLVM[6:0] SMBus Slave Address Mask. Defines which bits of register SMB0ADR are compared with an incoming address byte, and which bits are ignored. Any bit set to 1 in SLVM[6:0] enables compari- sons with the corresponding bit in SLV[6:0].
  • Page 206: Data Register

    C8051T620/1/6/7 & C8051T320/1/2/3 24.4.4. Data Register The SMBus Data register SMB0DAT holds a byte of serial data to be transmitted or one that has just been received. Software may safely read or write to the data register when the SI flag is set. Software should not attempt to access the SMB0DAT register when the SMBus is enabled and the SI flag is cleared to logic 0, as the interface may be in the process of shifting a byte of data into or out of the register.
  • Page 207: Smbus Transfer Modes

    C8051T620/1/6/7 & C8051T320/1/2/3 24.5. SMBus Transfer Modes The SMBus interface may be configured to operate as master and/or slave. At any particular time, it will be operating in one of the following four modes: Master Transmitter, Master Receiver, Slave Transmitter, or Slave Receiver.
  • Page 208: Read Sequence (Master)

    C8051T620/1/6/7 & C8051T320/1/2/3 24.5.2. Read Sequence (Master) During a read sequence, an SMBus master reads data from a slave device. The master in this transfer will be a transmitter during the address byte, and a receiver during all data bytes. The SMBus interface gener- ates the START condition and transmits the first byte containing the address of the target slave and the data direction bit.
  • Page 209: Write Sequence (Slave)

    C8051T620/1/6/7 & C8051T320/1/2/3 24.5.3. Write Sequence (Slave) During a write sequence, an SMBus master writes data to a slave device. The slave in this transfer will be a receiver during the address byte, and a receiver during all data bytes. When slave events are enabled (INH = 0), the interface enters Slave Receiver Mode when a START followed by a slave address and direc- tion bit (WRITE in this case) is received.
  • Page 210: Read Sequence (Slave)

    C8051T620/1/6/7 & C8051T320/1/2/3 24.5.4. Read Sequence (Slave) During a read sequence, an SMBus master reads data from a slave device. The slave in this transfer will be a receiver during the address byte, and a transmitter during all data bytes. When slave events are enabled (INH = 0), the interface enters Slave Receiver Mode (to receive the slave address) when a START followed by a slave address and direction bit (READ in this case) is received.
  • Page 211 C8051T620/1/6/7 & C8051T320/1/2/3 Table 24.5. SMBus Status Decoding With Hardware ACK Generation Disabled (EHACK = 0) Values to Values Read Write Current SMbus State Typical Response Options A master START was gener- Load slave address + R/W into 0 X 1100 1110 ated.
  • Page 212 C8051T620/1/6/7 & C8051T320/1/2/3 Table 24.5. SMBus Status Decoding With Hardware ACK Generation Disabled (EHACK = 0) (Continued) Values to Values Read Write Current SMbus State Typical Response Options A slave byte was transmitted; No action required (expecting 0 X 0001 NACK received.
  • Page 213 C8051T620/1/6/7 & C8051T320/1/2/3 Table 24.6. SMBus Status Decoding With Hardware ACK Generation Enabled (EHACK = 1) Values to Values Read Write Current SMbus State Typical Response Options A master START was gener- Load slave address + R/W into 0 X 1100 1110 ated.
  • Page 214 C8051T620/1/6/7 & C8051T320/1/2/3 Table 24.6. SMBus Status Decoding With Hardware ACK Generation Enabled (EHACK = 1) (Continued) Values to Values Read Write Current SMbus State Typical Response Options A slave byte was transmitted; No action required (expecting 0 X 0001 NACK received.
  • Page 215: Uart0

    C8051T620/1/6/7 & C8051T320/1/2/3 25. UART0 UART0 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 UART. Enhanced baud rate support allows a wide range of clock sources to generate standard baud rates (details in Section “25.1.
  • Page 216: Enhanced Baud Rate Generation

    C8051T620/1/6/7 & C8051T320/1/2/3 25.1. Enhanced Baud Rate Generation The UART0 baud rate is generated by Timer 1 in 8-bit auto-reload mode. The TX clock is generated by TL1; the RX clock is generated by a copy of TL1 (shown as RX Timer in Figure 25.2), which is not user- accessible.
  • Page 217: Operational Modes

    C8051T620/1/6/7 & C8051T320/1/2/3 25.2. Operational Modes UART0 provides standard asynchronous, full duplex communication. The UART mode (8-bit or 9-bit) is selected by the S0MODE bit (SCON0.7). Typical UART connection options are shown in Figure 25.3. RS-232 RS-232 C8051xxxx LEVEL XLTR C8051xxxx Figure 25.3.
  • Page 218: 9-Bit Uart

    C8051T620/1/6/7 & C8051T320/1/2/3 25.2.2. 9-Bit UART 9-bit UART mode uses a total of eleven bits per data byte: a start bit, 8 data bits (LSB first), a programma- ble ninth data bit, and a stop bit. The state of the ninth transmit data bit is determined by the value in TB80 (SCON0.3), which is assigned by user software.
  • Page 219: Multiprocessor Communications

    C8051T620/1/6/7 & C8051T320/1/2/3 25.3. Multiprocessor Communications 9-Bit UART mode supports multiprocessor communication between a master processor and one or more slave processors by special use of the ninth data bit. When a master processor wants to transmit to one or more slaves, it first sends an address byte to select the target(s).
  • Page 220: Sfr Definition 25.1. Scon0: Serial Port 0 Control

    C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 25.1. SCON0: Serial Port 0 Control Name S0MODE MCE0 REN0 TB80 RB80 Type Reset SFR Address = 0x98; Bit-Addressable Name Function S0MODE Serial Port 0 Operation Mode. Selects the UART0 Operation Mode. 0: 8-bit UART with Variable Baud Rate.
  • Page 221: Sfr Definition 25.2. Sbuf0: Serial (Uart0) Port Data Buffer

    C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 25.2. SBUF0: Serial (UART0) Port Data Buffer SBUF0[7:0] Name Type Reset SFR Address = 0x99 Name Function 7:0 SBUF0[7:0] Serial Data Buffer Bits 7–0 (MSB–LSB). This SFR accesses two registers; a transmit shift register and a receive latch register.
  • Page 222 C8051T620/1/6/7 & C8051T320/1/2/3 Table 25.1. Timer Settings for Standard Baud Rates Using The Internal 24.5 MHz Oscillator Frequency: 24.5 MHz Target Baud Rate Oscillator Timer Clock SCA1–SCA0 Timer 1 % Error Divide Source Reload Baud Rate (pre-scale Factor Value (hex)
  • Page 223: Uart1

    C8051T620/1/6/7 & C8051T320/1/2/3 26. UART1 UART1 is an asynchronous, full duplex serial port offering a variety of data formatting options. A dedicated baud rate generator with a 16-bit timer and selectable prescaler is included, which can generate a wide range of baud rates (details in Section “26.1. Baud Rate Generator” on page 223). A received data FIFO allows UART1 to receive up to three data bytes before data is lost and an overflow occurs.
  • Page 224: Table 26.1. Baud Rate Generator Settings For Standard Baud Rates

    C8051T620/1/6/7 & C8051T320/1/2/3 SYSCLK   -------------------------------------------------------------------------- - -- - --------------------- - Baud Rate   65536 (SBRLH1:SBRLL1) – Prescaler Equation 26.1. UART1 Baud Rate A quick reference for typical baud rates and system clock frequencies is given in Table 26.1.
  • Page 225: Data Format

    C8051T620/1/6/7 & C8051T320/1/2/3 26.2. Data Format UART1 has a number of available options for data formatting. Data transfers begin with a start bit (logic low), followed by the data bits (sent LSB-first), a parity or extra bit (if selected), and end with one or two stop bits (logic high).
  • Page 226: Configuration And Operation

    C8051T620/1/6/7 & C8051T320/1/2/3 26.3. Configuration and Operation UART1 provides standard asynchronous, full duplex communication. It can operate in a point-to-point serial communications application, or as a node on a multi-processor serial interface. To operate in a point- to-point application, where there are only two devices on the serial bus, the MCE1 bit in SMOD1 should be cleared to 0.
  • Page 227: Multiprocessor Communications

    C8051T620/1/6/7 & C8051T320/1/2/3 The SBUF1 register represents the oldest byte in the FIFO. After SBUF1 is read, the next byte in the FIFO is immediately loaded into SBUF1, and space is made available in the FIFO for another incoming byte. If enabled, an interrupt will occur when RI1 is set.
  • Page 228: Sfr Definition 26.1. Scon1: Uart1 Control

    C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 26.1. SCON1: UART1 Control OVR1 PERR1 THRE1 REN1 TBX1 RBX1 Name Type Reset SFR Address = 0xD2 Name Function OVR1 Receive FIFO Overrun Flag. This bit indicates a receive FIFO overrun condition, where an incoming character is discarded due to a full FIFO.
  • Page 229: Sfr Definition 26.2. Smod1: Uart1 Mode

    C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 26.2. SMOD1: UART1 Mode MCE1 S1PT[1:0] S1DL[1:0] XBE1 SBL1 Name Type Reset SFR Address = 0xE5 Name Function MCE1 Multiprocessor Communication Enable. 0: RI will be activated if stop bit(s) are 1. 1: RI will be activated if stop bit(s) and extra bit are 1 (extra bit must be enabled using XBE1).
  • Page 230: Sfr Definition 26.3. Sbuf1: Uart1 Data Buffer

    C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 26.3. SBUF1: UART1 Data Buffer SBUF1[7:0] Name Type Reset SFR Address = 0xD3 Name Description Write Read 7:0 SBUF1[7:0 Writing a byte to SBUF1 Reading SBUF1 retrieves Serial Data Buffer Bits. initiates the transmission. data from the receive...
  • Page 231: Sfr Definition 26.4. Sbcon1: Uart1 Baud Rate Generator Control

    C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 26.4. SBCON1: UART1 Baud Rate Generator Control Name Reserved SB1RUN Reserved Reserved Reserved Reserved SB1PS[1:0] Type Reset SFR Address = 0xAC Name Function Reserved Read = 0b. Must Write 0b. SB1RUN Baud Rate Generator Enable.
  • Page 232: Sfr Definition 26.6. Sbrll1: Uart1 Baud Rate Generator Low Byte

    C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 26.6. SBRLL1: UART1 Baud Rate Generator Low Byte SBRLL1[7:0] Name Type Reset SFR Address = 0xB4 Name Function 7:0 SBRLL1[7:0] UART1 Baud Rate Reload Low Bits. Low Byte of reload value for UART1 Baud Rate Generator.
  • Page 233: Enhanced Serial Peripheral Interface (Spi0)

    C8051T620/1/6/7 & C8051T320/1/2/3 27. Enhanced Serial Peripheral Interface (SPI0) The Enhanced Serial Peripheral Interface (SPI0) provides access to a flexible, full-duplex synchronous serial bus. SPI0 can operate as a master or slave device in both 3-wire or 4-wire modes, and supports mul- tiple masters and slaves on a single SPI bus.
  • Page 234: Signal Descriptions

    C8051T620/1/6/7 & C8051T320/1/2/3 27.1. Signal Descriptions The four signals used by SPI0 (MOSI, MISO, SCK, NSS) are described below. 27.1.1. Master Out, Slave In (MOSI) The master-out, slave-in (MOSI) signal is an output from a master device and an input to slave devices. It is used to serially transfer data from the master to the slave.
  • Page 235: Spi0 Master Mode Operation

    C8051T620/1/6/7 & C8051T320/1/2/3 27.2. SPI0 Master Mode Operation A SPI master device initiates all data transfers on a SPI bus. SPI0 is placed in master mode by setting the Master Enable flag (MSTEN, SPI0CN.6). Writing a byte of data to the SPI0 data register (SPI0DAT) when in master mode writes to the transmit buffer.
  • Page 236: Spi0 Slave Mode Operation

    C8051T620/1/6/7 & C8051T320/1/2/3 Master Slave MISO MISO Device Device MOSI MOSI GPIO Slave MISO MOSI Device Figure 27.4. 4-Wire Single Master Mode and 4-Wire Slave Mode Connection Diagram 27.3. SPI0 Slave Mode Operation When SPI0 is enabled and not configured as a master, it will operate as a SPI slave. As a slave, bytes are shifted in through the MOSI pin and out through the MISO pin by a master device controlling the SCK sig- nal.
  • Page 237: Spi0 Interrupt Sources

    C8051T620/1/6/7 & C8051T320/1/2/3 27.4. SPI0 Interrupt Sources When SPI0 interrupts are enabled, the following four flags will generate an interrupt when they are set to logic 1: All of the following bits must be cleared by software.  The SPI Interrupt Flag, SPIF (SPI0CN.7) is set to logic 1 at the end of each byte transfer. This flag can occur in all SPI0 modes.
  • Page 238: Figure 27.5. Master Mode Data/Clock Timing

    C8051T620/1/6/7 & C8051T320/1/2/3 (CKPOL=0, CKPHA=0) (CKPOL=0, CKPHA=1) (CKPOL=1, CKPHA=0) (CKPOL=1, CKPHA=1) MISO/MOSI Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 NSS (Must Remain High in Multi-Master Mode) Figure 27.5. Master Mode Data/Clock Timing (CKPOL=0, CKPHA=0)
  • Page 239: Spi Special Function Registers

    C8051T620/1/6/7 & C8051T320/1/2/3 (CKPOL=0, CKPHA=1) (CKPOL=1, CKPHA=1) MOSI Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MISO Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 NSS (4-Wire Mode) Figure 27.7.
  • Page 240: Sfr Definition 27.1. Spi0Cfg: Spi0 Configuration

    C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 27.1. SPI0CFG: SPI0 Configuration SPIBSY MSTEN CKPHA CKPOL SLVSEL NSSIN SRMT RXBMT Name Type Reset SFR Address = 0xA1 Name Function SPIBSY SPI Busy. This bit is set to logic 1 when a SPI transfer is in progress (master or slave mode).
  • Page 241: Sfr Definition 27.2. Spi0Cn: Spi0 Control

    C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 27.2. SPI0CN: SPI0 Control SPIF WCOL MODF RXOVRN NSSMD[1:0] TXBMT SPIEN Name Type Reset SFR Address = 0xF8; Bit-Addressable Name Function SPIF SPI0 Interrupt Flag. This bit is set to logic 1 by hardware at the end of a data transfer. If SPI interrupts are enabled, an interrupt will be generated.
  • Page 242: Sfr Definition 27.3. Spi0Ckr: Spi0 Clock Rate

    C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 27.3. SPI0CKR: SPI0 Clock Rate SCR[7:0] Name Type Reset SFR Address = 0xA2 Name Function SCR[7:0] SPI0 Clock Rate. These bits determine the frequency of the SCK output when the SPI0 module is configured for master mode operation. The SCK clock frequency is a divided ver-...
  • Page 243: Figure 27.8. Spi Master Timing (Ckpha = 0)

    C8051T620/1/6/7 & C8051T320/1/2/3 SCK* MCKH MCKL MISO MOSI * SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1. Figure 27.8. SPI Master Timing (CKPHA = 0) SCK* MCKH MCKL MISO MOSI * SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.
  • Page 244: Figure 27.10. Spi Slave Timing (Ckpha = 0)

    C8051T620/1/6/7 & C8051T320/1/2/3 SCK* MOSI MISO * SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1. Figure 27.10. SPI Slave Timing (CKPHA = 0) SCK* MOSI MISO * SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.
  • Page 245 C8051T620/1/6/7 & C8051T320/1/2/3 Table 27.1. SPI Slave Timing Parameters Parameter Description Units Master Mode Timing (See Figure 27.8 and Figure 27.9) SCK High Time 1 x T — MCKH SYSCLK SCK Low Time 1 x T — MCKL SYSCLK MISO Valid to SCK Shift Edge...
  • Page 246: Timers

    C8051T620/1/6/7 & C8051T320/1/2/3 28. Timers Each MCU includes four counter/timers: two are 16-bit counter/timers compatible with those found in the standard 8051, and two are 16-bit auto-reload timer for use with the SMBus or for general purpose use. These timers can be used to measure time intervals, count external events and generate periodic interrupt requests.
  • Page 247: Sfr Definition 28.1. Ckcon: Clock Control

    C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 28.1. CKCON: Clock Control T3MH T3ML T2MH T2ML SCA[1:0] Name Type Reset SFR Address = 0x8E Name Function T3MH Timer 3 High Byte Clock Select. Selects the clock supplied to the Timer 3 high byte (split 8-bit timer mode only).
  • Page 248: Timer 0 And Timer 1

    C8051T620/1/6/7 & C8051T320/1/2/3 28.1. Timer 0 and Timer 1 Each timer is implemented as a 16-bit register accessed as two separate bytes: a low byte (TL0 or TL1) and a high byte (TH0 or TH1). The Counter/Timer Control register (TCON) is used to enable Timer 0 and Timer 1 as well as indicate status.
  • Page 249: Mode 1: 16-Bit Counter/Timer

    C8051T620/1/6/7 & C8051T320/1/2/3 Setting TR0 does not force the timer to reset. The timer registers should be loaded with the desired initial value before the timer is enabled. TL1 and TH1 form the 13-bit register for Timer 1 in the same manner as described above for TL0 and TH0.
  • Page 250: Mode 3: Two 8-Bit Counter/Timers (Timer 0 Only)

    C8051T620/1/6/7 & C8051T320/1/2/3 TMOD IT01CF Pre-scaled Clock SYSCLK TCLK Interrupt (8 bits) Crossbar GATE0 Reload (8 bits) IN0PL INT0 Figure 28.2. T0 Mode 2 Block Diagram 28.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only) In Mode 3, Timer 0 is configured as two separate 8-bit counter/timers held in TL0 and TH0. The coun- ter/timer in TL0 is controlled using the Timer 0 control/status bits in TCON and TMOD: TR0, C/T0, GATE0 and TF0.
  • Page 251: Figure 28.3. T0 Mode 3 Block Diagram

    C8051T620/1/6/7 & C8051T320/1/2/3 TMOD Pre-scaled Clock Interrupt (8 bits) Interrupt SYSCLK (8 bits) Crossbar GATE0 IN0PL INT0 Figure 28.3. T0 Mode 3 Block Diagram Rev. 1.2...
  • Page 252: Sfr Definition 28.2. Tcon: Timer Control

    C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 28.2. TCON: Timer Control Name Type Reset SFR Address = 0x88; Bit-Addressable Name Function Timer 1 Overflow Flag. Set to 1 by hardware when Timer 1 overflows. This flag can be cleared by software but is automatically cleared when the CPU vectors to the Timer 1 interrupt service routine.
  • Page 253: Sfr Definition 28.3. Tmod: Timer Mode

    C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 28.3. TMOD: Timer Mode GATE1 C/T1 T1M[1:0] GATE0 C/T0 T0M[1:0] Name Type Reset SFR Address = 0x89 Name Function GATE1 Timer 1 Gate Control. 0: Timer 1 enabled when TR1 = 1 irrespective of INT1 logic level.
  • Page 254: Sfr Definition 28.4. Tl0: Timer 0 Low Byte

    C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 28.4. TL0: Timer 0 Low Byte TL0[7:0] Name Type Reset SFR Address = 0x8A Name Function TL0[7:0] Timer 0 Low Byte. The TL0 register is the low byte of the 16-bit Timer 0. SFR Definition 28.5. TL1: Timer 1 Low Byte...
  • Page 255: Sfr Definition 28.6. Th0: Timer 0 High Byte

    C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 28.6. TH0: Timer 0 High Byte TH0[7:0] Name Type Reset SFR Address = 0x8C Name Function TH0[7:0] Timer 0 High Byte. The TH0 register is the high byte of the 16-bit Timer 0. SFR Definition 28.7. TH1: Timer 1 High Byte...
  • Page 256: Timer 2

    C8051T620/1/6/7 & C8051T320/1/2/3 28.2. Timer 2 Timer 2 is a 16-bit timer formed by two 8-bit SFRs: TMR2L (low byte) and TMR2H (high byte). Timer 2 may operate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. The T2SPLIT bit (TMR2CN.3) defines the Timer 2 operation mode.
  • Page 257: 8-Bit Timers With Auto-Reload

    C8051T620/1/6/7 & C8051T320/1/2/3 28.2.2. 8-bit Timers with Auto-Reload When T2SPLIT is set, Timer 2 operates as two 8-bit timers (TMR2H and TMR2L). Both 8-bit timers oper- ate in auto-reload mode as shown in Figure 28.5. TMR2RLL holds the reload value for TMR2L; TMR2RLH holds the reload value for TMR2H.
  • Page 258: Low-Frequency Oscillator (Lfo) Capture Mode

    C8051T620/1/6/7 & C8051T320/1/2/3 28.2.3. Low-Frequency Oscillator (LFO) Capture Mode The Low-Frequency Oscillator Capture Mode allows the LFO clock to be measured against the system clock or an external oscillator source. Timer 2 can be clocked from the system clock, the system clock divided by 12, or the external oscillator divided by 8, depending on the T2ML (CKCON.4), and T2XCLK...
  • Page 259: Sfr Definition 28.8. Tmr2Cn: Timer 2 Control

    C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 28.8. TMR2CN: Timer 2 Control Name TF2H TF2L TF2LEN TF2CEN T2SPLIT T2XCLK Type Reset SFR Address = 0xC8; Bit-Addressable Name Function TF2H Timer 2 High Byte Overflow Flag. Set by hardware when the Timer 2 high byte overflows from 0xFF to 0x00. In 16 bit mode, this will occur when Timer 2 overflows from 0xFFFF to 0x0000.
  • Page 260: Sfr Definition 28.9. Tmr2Rll: Timer 2 Reload Register Low Byte

    C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 28.9. TMR2RLL: Timer 2 Reload Register Low Byte Name TMR2RLL[7:0] Type Reset SFR Address = 0xCA Name Function 7:0 TMR2RLL[7:0] Timer 2 Reload Register Low Byte. TMR2RLL holds the low byte of the reload value for Timer 2.
  • Page 261: Sfr Definition 28.12. Tmr2H Timer 2 High Byte

    C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 28.12. TMR2H Timer 2 High Byte Name TMR2H[7:0] Type Reset SFR Address = 0xCD Name Function 7:0 TMR2H[7:0] Timer 2 Low Byte. In 16-bit mode, the TMR2H register contains the high byte of the 16-bit Timer 2. In 8- bit mode, TMR2H contains the 8-bit high byte timer value.
  • Page 262: Timer 3

    C8051T620/1/6/7 & C8051T320/1/2/3 28.3. Timer 3 Timer 3 is a 16-bit timer formed by two 8-bit SFRs: TMR3L (low byte) and TMR3H (high byte). Timer 3 may operate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. The T3SPLIT bit (TMR3CN.3) defines the Timer 3 operation mode.
  • Page 263: 8-Bit Timers With Auto-Reload

    C8051T620/1/6/7 & C8051T320/1/2/3 28.3.2. 8-bit Timers with Auto-Reload When T3SPLIT is set, Timer 3 operates as two 8-bit timers (TMR3H and TMR3L). Both 8-bit timers oper- ate in auto-reload mode as shown in Figure 28.8. TMR3RLL holds the reload value for TMR3L; TMR3RLH holds the reload value for TMR3H.
  • Page 264: Low-Frequency Oscillator (Lfo) Capture Mode

    C8051T620/1/6/7 & C8051T320/1/2/3 28.3.3. Low-Frequency Oscillator (LFO) Capture Mode The Low-Frequency Oscillator Capture Mode allows the LFO clock to be measured against the system clock or an external oscillator source. Timer 3 can be clocked from the system clock, the system clock divided by 12, or the external oscillator divided by 8, depending on the T3ML (CKCON.6), and...
  • Page 265: Sfr Definition 28.13. Tmr3Cn: Timer 3 Control

    C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 28.13. TMR3CN: Timer 3 Control Name TF3H TF3L TF3LEN TF3CEN T3SPLIT T3XCLK[1:0] Type Reset SFR Address = 0x91 Name Function TF3H Timer 3 High Byte Overflow Flag. Set by hardware when the Timer 3 high byte overflows from 0xFF to 0x00. In 16 bit mode, this will occur when Timer 3 overflows from 0xFFFF to 0x0000.
  • Page 266: Sfr Definition 28.14. Tmr3Rll: Timer 3 Reload Register Low Byte

    C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 28.14. TMR3RLL: Timer 3 Reload Register Low Byte Name TMR3RLL[7:0] Type Reset SFR Address = 0x92 Name Function 7:0 TMR3RLL[7:0] Timer 3 Reload Register Low Byte. TMR3RLL holds the low byte of the reload value for Timer 3.
  • Page 267: Sfr Definition 28.17. Tmr3H Timer 3 High Byte

    C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 28.17. TMR3H Timer 3 High Byte Name TMR3H[7:0] Type Reset SFR Address = 0x95 Name Function TMR3H[7:0] Timer 3 High Byte. In 16-bit mode, the TMR3H register contains the high byte of the 16-bit Timer 3. In 8-bit mode, TMR3H contains the 8-bit high byte timer value.
  • Page 268: Programmable Counter Array

    C8051T620/1/6/7 & C8051T320/1/2/3 29. Programmable Counter Array The Programmable Counter Array (PCA0) provides enhanced timer functionality while requiring less CPU intervention than the standard 8051 counter/timers. The PCA consists of a dedicated 16-bit counter/timer and five 16-bit capture/compare modules. Each capture/compare module has its own associated I/O line (CEXn) which is routed through the Crossbar to Port I/O when enabled.
  • Page 269: Pca Counter/Timer

    C8051T620/1/6/7 & C8051T320/1/2/3 29.1. PCA Counter/Timer The 16-bit PCA counter/timer consists of two 8-bit SFRs: PCA0L and PCA0H. PCA0H is the high byte (MSB) of the 16-bit counter/timer and PCA0L is the low byte (LSB). Reading PCA0L automatically latches the value of PCA0H into a “snapshot” register; the following PCA0H read accesses this “snapshot” register.
  • Page 270: Pca0 Interrupt Sources

    C8051T620/1/6/7 & C8051T320/1/2/3 IDLE PCA0MD PCA0CN To SFR Bus PCA0L read Snapshot Register SYSCLK/12 SYSCLK/4 Timer 0 Overflow Overflow PCA0H PCA0L To PCA Interrupt System SYSCLK External Clock/8 To PCA Modules Figure 29.2. PCA Counter/Timer Block Diagram 29.2. PCA0 Interrupt Sources Figure 29.3 shows a diagram of the PCA interrupt tree.
  • Page 271: Capture/Compare Modules

    C8051T620/1/6/7 & C8051T320/1/2/3 (for n = 0 to 4) PCA0CPMn PCA0CN PCA0MD PCA0PWM PCA Counter/Timer 8, 9, Set 8, 9, 10, or 11 bit Operation 10 or 11-bit Overflow PCA Counter/Timer 16- bit Overflow ECCF0 EPCA0 PCA Module 0 Interrupt...
  • Page 272: Edge-Triggered Capture Mode

    C8051T620/1/6/7 & C8051T320/1/2/3 Table 29.2. PCA0CPM and PCA0PWM Bit Settings for PCA Capture/Compare Modules Operational Mode PCA0CPMn PCA0PWM Bit Number 7 6 5 4 3 2 1 0 7 6 5 4-2 Capture triggered by positive edge on CEXn X X 1 0 0 0 0 A 0 X B XXX XX...
  • Page 273: Software Timer (Compare) Mode

    C8051T620/1/6/7 & C8051T320/1/2/3 PCA Interrupt PCA0CPMn PCA0CN 0 0 0 x PCA0CPLn PCA0CPHn CEXn Capture Port I/O Crossbar PCA0L PCA0H Timebase Figure 29.4. PCA Capture Mode Diagram Note: The CEXn input signal must remain high or low for at least 2 system clock cycles to be recognized by the hardware.
  • Page 274: High-Speed Output Mode

    C8051T620/1/6/7 & C8051T320/1/2/3 Write to PCA0CPLn Reset Write to PCA0CPHn PCA Interrupt PCA0CPMn PCA0CN PCA0CPLn PCA0CPHn Enable Match 16-bit Comparator PCA0L PCA0H Timebase Figure 29.5. PCA Software Timer Mode Diagram 29.3.3. High-Speed Output Mode In High-Speed Output mode, a module’s associated CEXn pin is toggled each time a match occurs between the PCA Counter and the module's 16-bit capture/compare register (PCA0CPHn and PCA0CPLn).
  • Page 275: Frequency Output Mode

    C8051T620/1/6/7 & C8051T320/1/2/3 Write to PCA0CPLn Reset PCA0CPMn Write to PCA0CPHn PCA Interrupt PCA0CN PCA0CPLn PCA0CPHn Enable Match 16-bit Comparator TOGn Toggle CEXn Crossbar Port I/O PCA0L PCA0H Timebase Figure 29.6. PCA High-Speed Output Mode Diagram 29.3.4. Frequency Output Mode Frequency Output Mode produces a programmable-frequency square wave on the module’s associated...
  • Page 276: 8-Bit, 9-Bit, 10-Bit And 11-Bit Pulse Width Modulator Modes

    C8051T620/1/6/7 & C8051T320/1/2/3 Write to PCA0CPLn Reset PCA0CPMn Write to PCA0CPHn PCA0CPLn 8-bit Adder PCA0CPHn Adder Enable TOGn Toggle 0 0 0 CEXn 8-bit match Enable Crossbar Port I/O Comparator PCA Timebase PCA0L Figure 29.7. PCA Frequency Output Mode 29.3.5. 8-bit, 9-bit, 10-bit and 11-bit Pulse Width Modulator Modes Each module can be used independently to generate a pulse width modulated (PWM) output on its associ- ated CEXn pin.
  • Page 277: 9/10/11-Bit Pulse Width Modulator Mode

    C8051T620/1/6/7 & C8051T320/1/2/3 Write to PCA0CPLn Reset PCA0CPHn Write to PCA0CPHn COVF PCA0PWM PCA0CPMn PCA0CPLn 0 0 x 0 8-bit match CEXn Enable Crossbar Port I/O Comparator PCA Timebase PCA0L Overflow Figure 29.8. PCA 8-Bit PWM Mode Diagram 29.3.5.2. 9/10/11-bit Pulse Width Modulator Mode The duty cycle of the PWM output signal in 9/10/11-bit PWM mode should be varied by writing to an “Auto-...
  • Page 278: 16-Bit Pulse Width Modulator Mode

    C8051T620/1/6/7 & C8051T320/1/2/3 A 0% duty cycle may be generated by clearing the ECOMn bit to 0. Write to PCA0CPLn R/W when (Auto-Reload) PCA0PWM ARSEL = 1 Reset PCA0CPH:Ln (right-justified) Write to PCA0CPHn PCA0CPMn R/W when (Capture/Compare) ARSEL = 0 Set “N”...
  • Page 279: Watchdog Timer Mode

    C8051T620/1/6/7 & C8051T320/1/2/3 Write to PCA0CPLn Reset Write to PCA0CPHn PCA0CPMn PCA0CPHn PCA0CPLn 0 0 x 0 match CEXn Enable 16-bit Comparator Crossbar Port I/O PCA Timebase PCA0H PCA0L Overflow Figure 29.10. PCA 16-Bit PWM Mode 29.4. Watchdog Timer Mode A programmable watchdog timer (WDT) function is available through the PCA Module 4.
  • Page 280: Watchdog Timer Usage

    C8051T620/1/6/7 & C8051T320/1/2/3 PCA0MD PCA0CPH4 8-bit Match Reset Comparator Enable PCA0L Overflow PCA0CPL4 8-bit Adder PCA0H Adder Enable Write to PCA0CPH4 Figure 29.11. PCA Module 2 with Watchdog Timer Enabled Note that the 8-bit offset held in PCA0CPH4 is compared to the upper byte of the 16-bit PCA counter. This offset value is the number of PCA0L overflows before a reset.
  • Page 281: Register Descriptions For Pca0

    C8051T620/1/6/7 & C8051T320/1/2/3 timeout interval of 256 PCA clock cycles, or 3072 system clock cycles. Table 29.3 lists some example time- out intervals for typical system clocks. Table 29.3. Watchdog Timer Timeout Intervals System Clock (Hz) PCA0CPL4 Timeout Interval (ms) 12,000,000 65.5...
  • Page 282: Sfr Definition 29.1. Pca0Cn: Pca Control

    C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 29.1. PCA0CN: PCA Control Name CCF4 CCF3 CCF2 CCF1 CCF0 Type Reset SFR Address = 0xD8; Bit-Addressable Name Function PCA Counter/Timer Overflow Flag. Set by hardware when the PCA Counter/Timer overflows from 0xFFFF to 0x0000.
  • Page 283: Sfr Definition 29.2. Pca0Md: Pca Mode

    C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 29.2. PCA0MD: PCA Mode Name CIDL WDTE WDLCK CPS2 CPS1 CPS0 Type Reset SFR Address = 0xD9 Name Function CIDL PCA Counter/Timer Idle Control. Specifies PCA behavior when CPU is in Idle Mode. 0: PCA continues to function normally while the system controller is in Idle Mode.
  • Page 284: Sfr Definition 29.3. Pca0Pwm: Pca Pwm Configuration

    C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 29.3. PCA0PWM: PCA PWM Configuration Name ARSEL ECOV COVF CLSEL[1:0] Type Reset SFR Address = 0xF4 Name Function ARSEL Auto-Reload Register Select. This bit selects whether to read and write the normal PCA capture/compare registers (PCA0CPn), or the Auto-Reload registers at the same SFR addresses.
  • Page 285: Sfr Definition 29.4. Pca0Cpmn: Pca Capture/Compare Mode

    C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 29.4. PCA0CPMn: PCA Capture/Compare Mode Name PWM16n ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn Type Reset SFR Addresses: 0xDA (n = 0), 0xDB (n = 1), 0xDC (n = 2), 0xDD (n = 3), 0xDE (n = 4)
  • Page 286: Sfr Definition 29.5. Pca0L: Pca Counter/Timer Low Byte

    C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 29.5. PCA0L: PCA Counter/Timer Low Byte Name PCA0[7:0] Type Reset SFR Address = 0xF9 Name Function PCA0[7:0] PCA Counter/Timer Low Byte. The PCA0L register holds the low byte (LSB) of the 16-bit PCA Counter/Timer. Note: When the WDTE bit is set to 1, the PCA0L register cannot be modified by software. To change the contents of the PCA0L register, the Watchdog Timer must first be disabled.
  • Page 287: Sfr Definition 29.7. Pca0Cpln: Pca Capture Module Low Byte

    C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 29.7. PCA0CPLn: PCA Capture Module Low Byte Name PCA0CPn[7:0] Type Reset SFR Addresses: 0xFB (n = 0), 0xE9 (n = 1), 0xEB (n = 2), 0xED (n = 3), 0xFD (n = 4) Name Function PCA0CPn[7:0] PCA Capture Module Low Byte.
  • Page 288: C2 Interface

    C8051T620/1/6/7 & C8051T320/1/2/3 30. C2 Interface C8051T620/1/6/7 & C8051T320/1/2/3 devices include an on-chip Silicon Labs 2-Wire (C2) debug interface to allow EPROM programming and in-system debugging with the production part installed in the end appli- cation. The C2 interface operates using only two pins: a bi-directional data signal (C2D), and a clock input (C2CK).
  • Page 289 C8051T620/1/6/7 & C8051T320/1/2/3 C2 Register Definition 30.2. DEVICEID: C2 Device ID Name DEVICEID[7:0] Type Reset Varies Varies Varies Varies Varies Varies Varies Varies C2 Address: 0x00 Name Function 7:0 DEVICEID[7:0] Device ID. This read-only register returns the 8-bit device ID: 0x18 (C8051T620/621/320/321/322/323).
  • Page 290 C8051T620/1/6/7 & C8051T320/1/2/3 C2 Register Definition 30.4. DEVCTL: C2 Device Control Name DEVCTL[7:0] Type Reset C2 Address: 0x02 Name Function 7:0 DEVCTL[7:0] Device Control Register. This register is used to halt the device for EPROM operations via the C2 interface.
  • Page 291 C8051T620/1/6/7 & C8051T320/1/2/3 C2 Register Definition 30.6. EPDAT: C2 EPROM Data Name EPDAT[7:0] Type Reset C2 Address: 0xBF Name Function 7:0 EPDAT[7:0] C2 EPROM Data Register. This register is used to pass EPROM data during C2 EPROM operations. C2 Register Definition 30.7. EPSTAT: C2 EPROM Status...
  • Page 292 C8051T620/1/6/7 & C8051T320/1/2/3 C2 Register Definition 30.8. EPADDRH: C2 EPROM Address High Byte Name EPADDR[15:8] Type Reset C2 Address: 0xAF Name Function EPADDR[15:8] C2 EPROM Address High Byte. This register is used to set the EPROM address location during C2 EPROM oper- ations.
  • Page 293 C8051T620/1/6/7 & C8051T320/1/2/3 C2 Register Definition 30.10. CRC0: CRC Byte 0 Name CRC[7:0] Type Reset C2 Address: 0xA9 Name Function CRC[7:0] CRC Byte 0. A write to this register initiates a 16-bit CRC of one 256-byte block of EPROM mem- ory.
  • Page 294 C8051T620/1/6/7 & C8051T320/1/2/3 C2 Register Definition 30.12. CRC2: CRC Byte 2 Name CRC[23:16] Type Reset C2 Address: 0xAB Name Function 7:0 CRC[23:16] CRC Byte 2. See Section “18.4. Program Memory CRC” on page 115. C2 Register Definition 30.13. CRC3: CRC Byte 3...
  • Page 295: C2 Pin Sharing

    C8051T620/1/6/7 & C8051T320/1/2/3 30.2. C2 Pin Sharing The C2 protocol allows the C2 pins to be shared with user functions so that in-system debugging and EPROM programming functions may be performed. This is possible because C2 communication is typi- cally performed when the device is in the halt state, where all on-chip peripherals and user software are stalled.
  • Page 296: Document Change List

    C8051T620/1/6/7 & C8051T320/1/2/3 OCUMENT HANGE Revision 0.1 to Revision 1.0  Updated “Electrical Characteristics” on page 34. Revision 1.0 to Revision 1.1  Updated reset values for POWER, EMI0CF, VDM0CN, AMX0P, CPT0MX, and CPT1MX SFRs.  Updated Figure 21.1 on page 127.
  • Page 297 C8051T620/1/6/7 & C8051T320/1/2/3 OTES Rev. 1.2...
  • Page 298: Contact Information

    Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur.
  • Page 299 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Silicon Laboratories C8051T626-B-GM C8051T627-B-GM...

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