Silicon Laboratories Giant Gecko EFM32GG Manuals

Manuals and User Guides for Silicon Laboratories Giant Gecko EFM32GG. We have 1 Silicon Laboratories Giant Gecko EFM32GG manual available for free PDF download: Reference Manual

Silicon Laboratories Giant Gecko EFM32GG Reference Manual (843 pages)

Brand: Silicon Laboratories | Category: Microcontrollers | Size: 12 MB

Energy Friendly Microcontrollers
2
Typical Applications
2
EFM32GG Development
2
About this Document
3
Conventions
3
Register Access Types
3
Related Documentation
4
System Overview
5
Introduction
5
Block Diagram
5
Features
6
Energy Modes
7
Product Overview
8
EFM32GG Microcontroller Series
8
Device Revision
10
System Processor
12
Introduction
12
Features
12
Functional Description
13
Interrupt Operation
13
Interrupt Request Lines (IRQ)
13
Lcd
14
Vcmp
14
Memory and Bus System
15
Introduction
15
Ebi
15
Functional Description
16
Memory SRAM Area Set/Clear Bit
17
Memory System Core Peripherals
18
Memory Peripheral Area Bit Modification
18
Access to Low Energy Peripherals (Asynchronous Registers)
20
Memory Wait Cycles with Clock Equal or Faster than HFCORECLK
20
Memory Wait Cycles with Clock Slower than CPU
20
Write Operation to Low Energy Peripherals
21
Flash
22
Sram
23
Device Information (DI) Page
23
Device Information
23
DBG - Debug Interface
25
Introduction
25
Features
25
Functional Description
25
Debug Lock and Device Erase
26
Device Unlock
27
AAP Expansion
27
Register Map
28
Register Description
28
MSC - Memory System Controller
30
Introduction
30
Instruction Cache
30
Features
31
Functional Description
31
Lock Bits
32
Register Map
38
Register Description
38
DMA - DMA Controller
48
Introduction
48
Features
48
Block Diagram
49
Functional Description
50
DMA Cycle Types
53
Channel_Cfg for a Primary Data Structure, in Memory Scatter-Gather Mode
57
Memory Scatter-Gather Example
58
Channel_Cfg for a Primary Data Structure, in Peripheral Scatter-Gather Mode
59
Peripheral Scatter-Gather Example
60
Copy
60
Channel_Cfg Bit Assignments
64
Examples
70
Register Map
71
Bus
71
Register Description
72
RMU - Reset Management Unit
97
Introduction
97
Features
97
Functional Description
97
Register Map
102
Register Description
102
EMU - Energy Management Unit
105
Introduction
105
Features
105
Functional Description
106
EMU Overview
106
Backup Power Domain Overview
112
Register Map
117
Register Description
117
CMU - Clock Management Unit
126
Introduction
126
Features
126
Functional Description
127
CMU Overview
128
CMU Switching from HFRCO to HFXO before HFXO Is Ready
131
CMU Switching from HFRCO to HFXO after HFXO Is Ready
132
Continuous Calibration (CONT=1)
134
Configuration for Operating Frequencies
135
Register Map
136
Lcd
136
Register Description
137
WDOG - Watchdog Timer
159
Introduction
159
Features
159
Functional Description
159
WDOG Timeout Equation
160
Register Map
161
Register Description
161
PRS - Peripheral Reflex System
164
Introduction
164
Features
164
Functional Description
164
PRS Overview
165
Register Map
169
Register Description
169
EBI - External Bus Interface
175
Introduction
175
Features
175
Functional Description
176
EBI Overview
177
EBI Non-Multiplexed 8-Bit Data, 8-Bit Address Read Operation
178
EBI Non-Multiplexed 8-Bit Data, 8-Bit Address Write Operation
178
EBI Multiplexed 16-Bit Data, 16-Bit Address Read Operation
179
EBI Multiplexed 16-Bit Data, 16-Bit Address Write Operation
179
EBI Multiplexed 8-Bit Data, 24-Bit Address Read Operation
180
EBI Multiplexed 8-Bit Data, 24-Bit Address Write Operation
180
EBI Non-Multiplexed 16-Bit Data Read Operation with Extended Address
181
EBI Non-Multiplexed 16-Bit Data Write Operation with Extended Address
181
EBI Page Mode Read Operation for D8A8 Addressing Mode
182
EBI Page Mode Read Operation for D16A16ALE Addressing Mode
182
EBI Page Mode Read Operation for D8A24ALE Addressing Mode
183
EBI Page Mode Read Operation for D16 Addressing Mode
183
EBI 16-Bit Data Multiplexed Read Operation Using Extended Addressing
184
EBI 16-Bit Data Multiplexed Write Operation Using Extended Addressing
184
EBI Multiplexed Read Operation with Reduced Length Strobes
186
EBI Multiplexed Write Operation with Reduced Length Strobes
186
EBI Connection with Standard NAND Flash
192
EBI Connection with Chip Enable Don't Care NAND Flash
193
EBI NAND Flash Register Select
193
EBI NAND Flash Data Input Timing
195
EBI NAND Flash Data Output Timing
196
EBI NAND Flash Read Timing
196
EBI NAND Flash Read/Write Timing Requirements
196
EBI ECC Generation
198
EBI EBI_ECCPARITY Format
199
EBI EBI_ECCPARITY Valid Bits
199
EBI TFT Total Width
200
EBI TFT Total Height
200
EBI TFT Size
201
EBI TFT Direct Drive from Internal Memory
202
EBI TFT Direct Drive from External Memory (Non-Multiplexed Address/Data)
203
EBI TFT Direct Drive from External Memory (Multiplexed Address/Data)
203
EBI Alpha Blending Equation
205
EBI In-Place Alpha Blending into External Memory
206
EBI Alpha Blending into External Memory with Background Color1 from Register
206
EBI Internal Alpha Blending from Registers into Register
206
EBI TFT Pixel Timing
208
EBI TFT Direct Drive Internal Timing
208
EBI TFT Direct Drive External Timing
208
EBI TFT Pixel Timing: EBI_DCLK Driven off Positive Edge Internal Clock
209
EBI TFT Pixel Timing: EBI_DCLK Driven off Negative Edge Internal Clock
210
Pin Configuration
210
Register Map
212
Register Description
213
USB - Universal Serial Bus Controller
242
Introduction
242
Features
242
USB System Description
243
Bus-Powered Device
245
Self-Powered Device
246
OTG Dual Role Device (5V)
246
USB Core Description
249
Host Programming Operations
256
Normal Bulk/Control OUT/SETUP and Bulk/Control in Transactions in Slave Mode
262
Normal Bulk/Control OUT/SETUP and Bulk/Control in Transactions in DMA Mode
267
Interrupt Service Routine for Bulk/Control out Transaction in DMA Mode
268
Normal Interrupt OUT/IN Transactions in Slave Mode
272
Normal Interrupt OUT/IN Transactions in DMA Mode
276
Normal Isochronous OUT/IN Transactions in Slave Mode
280
Normal Isochronous OUT/IN Transactions in DMA Mode
283
Two-Stage Control Transfer
293
Host
294
Slave Mode Bulk out Transaction
298
Isochronous out Core Internal Flow for Periodic Transfer Interrupt Feature
305
Bulk in Stall
306
Slave Mode Bulk in Transaction
314
Slave Mode Bulk in Transfer (Pipelined Transaction)
315
Slave Mode Bulk in Two-Endpoint Transfer
316
HNP When the Core Is an A-Device
329
HNP When the Core Is a B-Device
330
Register Map
349
Register Description
353
C - Inter-Integrated Circuit Interface
415
Introduction
415
Features
415
Functional Description
416
C Pull-Up Resistor Equation
416
C START and STOP Conditions
417
C High and Low Periods for Low CLKDIV
420
C Maximum Transmission Rate
420
C High and Low Cycles Equations
420
Maximum Data Hold Time
420
C Master State Machine
423
C Interactions in Prioritized Order
424
C Slave State Machine
430
Register Map
437
Register Description
437
USART - Universal Synchronous Asynchronous Receiver/Transmitter
449
Introduction
449
Features
449
Functional Description
450
USART Overview
450
USART Asynchronous Frame Format
451
USART Asynchronous Vs. Synchronous Mode
451
USART Pin Usage
451
USART Data Bits
452
USART Stop Bits
452
USART Baud Rate
453
USART Desired Baud Rate
453
USART Sampling of Start and Data Bits
458
USART Sampling of Stop Bits When Number of Stop Bits Are 1 or more
459
USART Transmission of Large Frames
462
USART ISO 7816 Data Frame Without Error
464
USART ISO 7816 Data Frame with Error
465
USART SPI Modes
466
USART Synchronous Mode Bit Rate
466
USART Synchronous Mode Clock Division Factor
466
USART I2S Modes
469
Register Map
475
Register Description
475
UART - Universal Asynchronous Receiver/Transmitter
495
Introduction
495
Features
495
Functional Description
496
Register Description
496
Register Map
496
LEUART - Low Energy Universal Asynchronous Receiver/Transmitter
497
Introduction
497
Features
497
Functional Description
498
LEUART Baud Rates
500
LEUART Baud Rate Equation
500
LEUART CLKDIV Equation
500
LEUART Optimal Sampling Point
504
LEUART Actual Sampling Point
504
Register Map
509
Register Description
509
TIMER - Timer/Counter
523
Introduction
523
Features
523
Functional Description
524
TIMER Counter Response in X2 Decoding Mode
529
TIMER Counter Response in X4 Decoding Mode
529
TIMER Rotational Position Equation
529
TIMER Up-Count PWM Resolution Equation
534
TIMER Up-Count PWM Frequency Equation
534
TIMER Up-Count Duty Cycle Equation
535
TIMER 2X PWM Resolution Equation
535
TIMER 2X Mode PWM Frequency Equation( Up-Count)
535
TIMER 2X Mode Duty Cycle Equation
535
TIMER Up/Down-Count PWM Resolution Equation
536
TIMER Up/Down-Count PWM Frequency Equation
536
TIMER Up/Down-Count Duty Cycle Equation
536
TIMER 2X PWM Resolution Equation
536
TIMER 2X Mode PWM Frequency Equation( Up/Down-Count)
537
TIMER 2X Mode Duty Cycle Equation
537
TIMER Events
541
Register Map
542
Register Description
543
RTC - Real Time Counter
561
Introduction
561
Features
561
Functional Description
562
RTC Frequency Equation
562
Register Map
565
Register Description
565
BURTC - Backup Real Time Counter
570
Introduction
570
Features
570
Functional Description
571
BURTC Frequency Equation
571
Low Power Mode Compare Match Resolution
572
Register Map
575
Register Description
575
LETIMER - Low Energy Timer
585
Introduction
585
Features
585
Functional Description
586
LETIMER Clock Frequency
591
Register Map
599
Register Description
599
PCNT - Pulse Counter
608
Introduction
608
Features
608
Functional Description
608
Absolute Position with Hysteresis and Even TOP Value
611
Absolute Position with Hysteresis and Odd TOP Value
611
Register Map
614
Register Description
614
LESENSE - Low Energy Sensor Interface
623
Introduction
623
Features
623
Functional Description
624
Scan Frequency
626
Bias Configuration
633
LESENSE Decoder Configuration
638
Register Map
639
Register Description
640
ACMP - Analog Comparator
669
Introduction
669
Features
669
VDD Scaled
669
Functional Description
670
Bias Configuration
671
Register Map
674
Register Description
674
VCMP - Voltage Comparator
680
Introduction
680
Features
680
Functional Description
681
VCMP Overview
681
DD Trigger Level
682
Register Map
684
Register Description
684
ADC - Analog to Digital Converter
688
Introduction
688
Features
688
Functional Description
689
ADC Overview
690
ADC Total Conversion Time (in ADC_CLK Cycles) Per Output
690
ADC Conversion Timing
691
ADC Temperature Measurement
693
ADC Conversion Tailgating
695
Calibration Register Effect
698
Register Map
699
Register Description
699
DAC - Digital to Analog Converter
712
Introduction
712
Features
712
Functional Description
713
DAC Overview
713
DAC Clock Prescaling
714
DAC Single Ended Output Voltage
715
DAC Differential Output Voltage
715
DAC Sine Mode
716
DAC Sine Generation
716
Register Map
718
Register Description
718
OPAMP - Operational Amplifier
733
Introduction
733
Features
733
Functional Description
734
OPAMP Overview
735
Voltage Follower Unity Gain Overview
737
General Opamp Mode Configuration
737
Voltage Follower Unity Gain Configuration
737
Inverting Input PGA Overview
738
Non-Inverting PGA Overview
738
Inverting Input PGA Configuration
738
Non-Inverting PGA Configuration
738
Cascaded Inverting PGA Overview
739
Cascaded Inverting PGA Configuration
739
Cascaded Non-Inverting PGA Overview
740
Cascaded Non-Inverting PGA Configuration
740
Two Op-Amp Differential Amplifier Overview
741
Three Op-Amp Differential Amplifier Overview
742
Three Opamp Differential Amplifier Gain Programming
742
Three Opamp Differential Amplifier Configuration
742
Register Description
743
Register Map
743
Dual Buffer ADC Driver Overview
743
Dual Buffer ADC Driver Configuration
743
AES - Advanced Encryption Standard Accelerator
744
Introduction
744
Features
744
Functional Description
744
Register Map
748
Register Description
748
GPIO - General Purpose Input/Output
756
Introduction
756
Features
756
Functional Description
757
Pin Configuration
758
Open-Drain
759
Register Map
764
Register Description
765
LCD - Liquid Crystal Display Driver
782
Introduction
782
Features
782
Functional Description
783
LCD Block Diagram
783
LCD 1/2 Bias and Duplex Multiplexing - LCD_SEG0
786
LCD 1/3 Bias and Duplex Multiplexing - LCD_SEG0
788
LCD 1/2 Bias and Triplex Multiplexing - LCD_SEG0
790
LCD 1/3 Bias and Triplex Multiplexing - LCD_SEG0
792
LCD 1/3 Bias and Quadruplex Multiplexing - LCD_SEG0
795
LCD Contrast
796
LCD Frame Rate Calculation
800
LCD Event Frequency Equation
802
Register Map
806
Register Description
806
Revision History
822
Revision 1.20
822
Revision 1.10
822
Revision 1.00
823
Revision 0.96
823
Revision 0.95
824
Revision 0.90
824
Abbreviations
826
Disclaimer and Trademarks
828
Disclaimer
828
Trademark Information
828
Contact Information
829

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