Silicon Laboratories C8051T620 Manual page 9

Figure 20.2. Power-On and VDD Monitor Reset Timing ....................................... 122
Figure 21.1. Oscillator Options .............................................................................. 127
Figure 21.2. External Crystal Example .................................................................. 135
Figure 22.1. Port I/O Functional Block Diagram .................................................... 138
Figure 22.2. Port I/O Cell Block Diagram .............................................................. 139
Figure 22.3. Priority Crossbar Decoder Potential Pin Assignments ...................... 143
Figure 22.4. Priority Crossbar Decoder Example 1-No Skipped Pins ................. 144
Figure 22.5. Priority Crossbar Decoder Example 2-Skipping Pins ...................... 145
Figure 23.1. USB0 Block Diagram ......................................................................... 160
Figure 23.2. USB0 Register Access Scheme ........................................................ 163
Figure 23.3. C8051T620/1 and C8051T320/1/2/3 USB FIFO Allocation ............... 169
Figure 23.4. C8051T626/7 USB FIFO Allocation .................................................. 170
Figure 24.1. SMBus Block Diagram ...................................................................... 194
Figure 24.2. Typical SMBus Configuration ............................................................ 195
Figure 24.3. SMBus Transaction ........................................................................... 196
Figure 24.4. Typical SMBus SCL Generation ........................................................ 198
Figure 24.5. Typical Master Write Sequence ........................................................ 207
Figure 24.6. Typical Master Read Sequence ........................................................ 208
Figure 24.7. Typical Slave Write Sequence .......................................................... 209
Figure 24.8. Typical Slave Read Sequence .......................................................... 210
Figure 25.1. UART0 Block Diagram ...................................................................... 215
Figure 25.2. UART0 Baud Rate Logic ................................................................... 216
Figure 25.3. UART Interconnect Diagram ............................................................. 217
Figure 25.4. 8-Bit UART Timing Diagram .............................................................. 217
Figure 25.5. 9-Bit UART Timing Diagram .............................................................. 218
Figure 25.6. UART Multi-Processor Mode Interconnect Diagram ......................... 219
Figure 26.1. UART1 Block Diagram ...................................................................... 223
Figure 26.2. UART1 Timing Without Parity or Extra Bit ......................................... 225
Figure 26.3. UART1 Timing With Parity ................................................................ 225
Figure 26.4. UART1 Timing With Extra Bit ............................................................ 225
Figure 26.5. Typical UART Interconnect Diagram ................................................. 226
Figure 26.6. UART Multi-Processor Mode Interconnect Diagram ......................... 227
Figure 27.1. SPI Block Diagram ............................................................................ 233
Figure 27.2. Multiple-Master Mode Connection Diagram ...................................... 235
Figure 27.3. 3-Wire Single Master and 3-Wire Single Slave Mode 
Connection Diagram ........................................................................................ 235
Figure 27.4. 4-Wire Single Master Mode and 4-Wire Slave Mode 
Connection Diagram ........................................................................................ 236
Figure 27.5. Master Mode Data/Clock Timing ....................................................... 238
Figure 27.6. Slave Mode Data/Clock Timing (CKPHA = 0) ................................... 238
Figure 27.7. Slave Mode Data/Clock Timing (CKPHA = 1) ................................... 239
Figure 27.8. SPI Master Timing (CKPHA = 0) ....................................................... 243
Figure 27.9. SPI Master Timing (CKPHA = 1) ....................................................... 243
Figure 27.10. SPI Slave Timing (CKPHA = 0) ....................................................... 244
C8051T620/1/6/7 & C8051T320/1/2/3
Rev. 1.2 9