Fifo Access; Table 23.3. Fifo Configurations - Silicon Laboratories C8051T620 Manual

Table 23.3. FIFO Configurations

Endpoint Split Mode
Number Enabled?
0 N/A
N
1
Y
N
2
Y
N
3
Y

23.5.1. FIFO Access

Each endpoint FIFO is accessed through a corresponding FIFOn register. A read of an endpoint FIFOn
register unloads one byte from the FIFO; a write of an endpoint FIFOn register loads one byte into the end-
point FIFO. When an endpoint FIFO is configured for Split Mode, a read of the endpoint FIFOn register
unloads one byte from the OUT endpoint FIFO; a write of the endpoint FIFOn register loads one byte into
the IN endpoint FIFO.
USB Register Definition 23.6. FIFOn: USB0 Endpoint FIFO Access
Bit 7
Name
Type
0
Reset
USB Register Address = 0x20-0x23
Bit Name
7:0 FIFODATA[7:0] Endpoint FIFO Access Bits.
USB Addresses 0x20-0x23 provide access to the 4 pairs of endpoint FIFOs:
0x20: Endpoint 0
0x21: Endpoint 1
0x22: Endpoint 2
0x23: Endpoint 3
Writing to the FIFO address loads data into the IN FIFO for the corresponding
endpoint. Reading from the FIFO address unloads data from the OUT FIFO for
the corresponding endpoint.
C8051T620/1/6/7 & C8051T320/1/2/3
Maximum IN Packet Size
(Double Buffer Disabled /
Enabled)
64 / 32
128 / 64
256 / 128
6 5 4
FIFODATA[7:0]
0 0 0
Rev. 1.2
Maximum OUT Packet Size
(Double Buffer Disabled /
64
128 / 64
256 / 128
512 / 256
3 2
R/W
0 0
Function
Enabled)
64 / 32
128 / 64
256 / 128
1 0
0 0
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