Sfr Definition 27.3. Spi0Ckr: Spi0 Clock Rate; Sfr Definition 27.4. Spi0Dat: Spi0 Data - Silicon Laboratories C8051T620 Manual

C8051T620/1/6/7 & C8051T320/1/2/3

SFR Definition 27.3. SPI0CKR: SPI0 Clock Rate

Bit 7
Name
Type
0
Reset
SFR Address = 0xA2
Bit Name
7:0 SCR[7:0]
SPI0 Clock Rate.
These bits determine the frequency of the SCK output when the SPI0 module is
configured for master mode operation. The SCK clock frequency is a divided ver-
sion of the system clock, and is given in the following equation, where SYSCLK is
the system clock frequency and SPI0CKR is the 8-bit value held in the SPI0CKR
register.
f
SCK
for 0 <= SPI0CKR <= 255
Example: If SYSCLK = 2 MHz and SPI0CKR = 0x04,
f
SCK
f

SFR Definition 27.4. SPI0DAT: SPI0 Data

Bit 7
Name
Type
0
Reset
SFR Address = 0xA3
Bit Name
7:0 SPI0DAT[7:0] SPI0 Transmit and Receive Data.
The SPI0DAT register is used to transmit and receive SPI0 data. Writing data to
SPI0DAT places the data into the transmit buffer and initiates a transfer when in
Master Mode. A read of SPI0DAT returns the contents of the receive buffer.
242
6 5 4
0 0 0
SYSCLK
---------------------------------------------------------- -
=
 
2 SPI0CKR[7:0]
2000000
------------------------- -
=
  
2 4 + 1
= 200kHz
SCK
6 5 4
SPI0DAT[7:0]
0 0 0
Rev. 1.2
3 2
SCR[7:0]
R/W
0 0
Function

+ 1
3 2
R/W
0 0
Function
1 0
0 0
1 0
0 0