Interrupts - Silicon Laboratories C8051T620 Manual

C8051T620/1/6/7 & C8051T320/1/2/3

23.8. Interrupts

The read-only USB0 interrupt flags are located in the USB registers shown in USB Register
Definition 23.11 through USB Register Definition 23.13. The associated interrupt enable bits are located in
the USB registers shown in USB Register Definition 23.14 through USB Register Definition 23.16. A USB0
interrupt is generated when any of the USB interrupt flags is set to 1. The USB0 interrupt is enabled via the
EIE1 SFR (see Section "17. Interrupts" on page 101).
Important Note: Reading a USB interrupt flag register resets all flags in that register to 0.
USB Register Definition 23.11. IN1INT: USB0 IN Endpoint Interrupt
Bit 7
Name
R
Type
0
Reset
USB Register Address = 0x02
Bit Name
7:4 Unused Read = 0000b. Write = don't care.
3 IN3
IN Endpoint 3 Interrupt-Pending Flag.
This bit is cleared when software reads the IN1INT register.
0: IN Endpoint 3 interrupt inactive.
1: IN Endpoint 3 interrupt active.
2 IN2
IN Endpoint 2 Interrupt-Pending Flag.
This bit is cleared when software reads the IN1INT register.
0: IN Endpoint 2 interrupt inactive.
1: IN Endpoint 2 interrupt active.
1 IN1
IN Endpoint 1 Interrupt-Pending Flag.
This bit is cleared when software reads the IN1INT register.
0: IN Endpoint 1 interrupt inactive.
1: IN Endpoint 1 interrupt active.
0 EP0
Endpoint 0 Interrupt-Pending Flag.
This bit is cleared when software reads the IN1INT register.
0: Endpoint 0 interrupt inactive.
1: Endpoint 0 interrupt active.
176
6 5 4
R R R
0 0 0
Rev. 1.2
3 2
IN3 IN2
R R
0 0
Function
1 0
IN1 EP0
R R
0 0