Enhanced Baud Rate Generation; Figure 25.2. Uart0 Baud Rate Logic - Silicon Laboratories C8051T620 Manual

C8051T620/1/6/7 & C8051T320/1/2/3

25.1. Enhanced Baud Rate Generation

The UART0 baud rate is generated by Timer 1 in 8-bit auto-reload mode. The TX clock is generated by
TL1; the RX clock is generated by a copy of TL1 (shown as RX Timer in Figure 25.2), which is not user-
accessible. Both TX and RX Timer overflows are divided by two to generate the TX and RX baud rates.
The RX Timer runs when Timer 1 is enabled, and uses the same reload value (TH1). However, an
RX Timer reload is forced when a START condition is detected on the RX pin. This allows a receive to
begin any time a START is detected, independent of the TX Timer state.
Start
Detected
Timer 1 should be configured for Mode 2, 8-bit auto-reload (see Section "28.1.3. Mode 2: 8-bit Coun-
ter/Timer with Auto-Reload" on page 249). The Timer 1 reload value should be set so that overflows will
occur at two times the desired UART baud rate frequency. Note that Timer 1 may be clocked by one of six
sources: SYSCLK, SYSCLK/4, SYSCLK/12, SYSCLK/48, the external oscillator clock/8, or an external
input T1. For any given Timer 1 clock source, the UART0 baud rate is determined by Equation 25.1-A and
Equation 25.1-B.
A)
B)
Where T1 is the frequency of the clock supplied to Timer 1, and T1H is the high byte of Timer 1 (reload
CLK
value). Timer 1 clock frequency is selected as described in Section "28. Timers" on page 246. A quick ref-
erence for typical baud rates and system clock frequencies is given in Table 25.1 through Table 25.2. The
internal oscillator may still generate the system clock when the external oscillator is driving Timer 1.
216
Timer 1
Overflow
TL1
TH1
Overflow
RX Timer

Figure 25.2. UART0 Baud Rate Logic

1

-- -
UARTBaudRate =
2
T1_Overflow_Rate =
Equation 25.1. UART0 Baud Rate
Rev. 1.2
UART
2
TX Clock
2
RX Clock
T1_Overflow_Rate
T1
CLK
------------------------- -
256 TH1 –