Port Input/Output; Figure 22.1. Port I/O Functional Block Diagram - Silicon Laboratories C8051T620 Manual

C8051T620/1/6/7 & C8051T320/1/2/3

22. Port Input/Output

Digital and analog resources are available through 21, 24, or 25 I/O pins, depending on the specific device.
Port pins P0.0-P2.7 can be defined as general-purpose I/O (GPIO), assigned to one of the internal digital
resources, or assigned to an analog function as shown in Figure 22.3. Port pin P3.0 on can be used as
GPIO and is shared with the C2 Interface Data signal (C2D). The designer has complete control over
which functions are assigned, limited only by the number of physical I/O pins. This resource assignment
flexibility is achieved through the use of a Priority Crossbar Decoder. Note that the state of a Port I/O pin
can always be read in the corresponding Port latch, regardless of the Crossbar settings.
The Crossbar assigns the selected internal digital resources to the I/O pins based on the Priority Decoder
(Figure 22.4). The registers XBR0, XBR1, and XBR2, defined in SFR Definition 22.1, SFR Definition 22.2,
and SFR Definition 22.2, are used to select internal digital functions.
All Port I/Os are 5 V tolerant (refer to Figure 22.2 for the Port cell circuit). The Port I/O cells are configured
as either push-pull or open-drain in the Port Output Mode registers (PnMDOUT, where n = 0,1). Complete
Electrical Specifications for Port I/O are given in Table 7.3 on page 36.
Highest
UART0
Priority
SPI
SMBus
CP0
Outputs
CP1
Outputs
SYSCLK
PCA
T0, T1
Lowest
UART1
Priority
P0
P1
P2
P3
138
XBR2, PnSKIP
2
4
2
2
2
6
2
2
8
(P0.0-P0.7)
8
(P1.0-P1.7)
7
(P2.0-P2.6)
1
(P3.0)

Figure 22.1. Port I/O Functional Block Diagram

Rev. 1.2
XBR0, XBR1, Port Match
P0MASK, P0MAT
Registers P1MASK, P1MAT
External Interrupts
Priority
Decoder
PnMDIN Registers
P0
Digital
8
I/O
Crossbar
Cells
P1
8
I/O
Cells
P2
7
I/O
Cells
P3
I/O
Cell
To Analog Peripherals
(ADC0, CP0, CP1, VREF,
EXTCLK)
EX0 and EX1
PnMDOUT,
P0.0
P0.7
P1.0
P1.7
P2.0
P2.7
P3.0