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Silicon Laboratories C8051T60x-DK User Manual
Silicon Laboratories C8051T60x-DK User Manual

Silicon Laboratories C8051T60x-DK User Manual

C8051t60x development kit

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1. Kit Contents
The C8051T60x Development Kit contains the following items:
C8051T600 Main Board
C8051T600 SOIC Socket Daughter Board for programming SOIC devices
C8051T600 Emulation Daughter Board with C8051F300 installed
(5) C8051T600-GS Samples
C8051T60x Development Kit Quick-Start Guide
Silicon Laboratories IDE and Product Information CD-ROM. CD content includes:
Silicon Laboratories Integrated Development Environment (IDE)
Evaluation Version of Keil 8051 Development Tools (macro assembler, linker, 'C' Compiler)
Source code examples and register definition files
Documentation
AC to DC Universal Power Adapter
USB Cable
RS-232 Cable
Also available for purchase separately is a C8051T600 QFN Socket Daughter Board for programming QFN
devices.
2. About the Daughter Boards
The C8051T60x Development Kit includes two daughter boards: an Emulation Daughter Board (EDB) and an SOIC
Socket Daughter Board (SOIC-DB). The EDB has a C8051F300 device installed, which is a Flash-based device
that can be used for the majority of C8051T60x code development. The SOIC-DB and the QFN-DB (available
separately) are intended to allow both the programming of multiple C8051T60x devices, as well as system-level
debugging of these devices. Once a C8051T60x device has been programmed, it cannot be erased, so it is
advisable to use the C8051F300 for the majority of code development. Refer to Application Note "AN280:
Differences Between the C8051F300 and the C8051T60x Device Family" for more details on how the C8051F300
can be used to develop code for the C8051T60x device family.
3. Hardware Setup
Refer to Figure 1 for a diagram of the hardware configuration.
1. Attach the desired daughter board to the main board at connectors P1 and P2.
2. If using the SOIC Socket daughter board or the QFN Socket daughter board, place the device to be
programmed into the socket.
3. Connect the AC to DC Power Adapter to connector P3 on the main board.
4. Connect the main board to a PC running the Silicon Laboratories IDE using the USB Cable.
Notes:
Use the Reset icon in the IDE to reset the target when connected during a debug session.
Remove power from the main board and remove the USB cable before removing a daughter board from the
main board. Connecting or disconnecting a daughter board when the power adapter or USB cable are
connected can damage the main board, the daughter board, or the socketed device.
Likewise, remove power from the main board and remove the USB cable before removing a C8051T60x device
from the socket. Inserting or removing a device from the socket when the power adapter or USB cable are
connected can damage the main board, the daughter board, or the socketed device.
Rev. 0.1 1/07
E V E L O P M E N T
Copyright © 2007 by Silicon Laboratories
C8051T 60x-DK
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C8051T60x-DK

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Summary of Contents for Silicon Laboratories C8051T60x-DK

  • Page 1 3. Connect the AC to DC Power Adapter to connector P3 on the main board. 4. Connect the main board to a PC running the Silicon Laboratories IDE using the USB Cable. Notes: Use the Reset icon in the IDE to reset the target when connected during a debug session.
  • Page 2: Usb Cable

    Figure 1. Hardware Setup (Emulation Daughter Board Shown) 4. Software Setup The included CD-ROM contains the Silicon Laboratories Integrated Development Environment (IDE), Keil software 8051 tools and additional documentation. Insert the CD-ROM into your PC’s CD-ROM drive. An installer will automatically launch, allowing you to install the IDE software or read documentation by clicking buttons on the Installation Panel.
  • Page 3 ROM for additional information on using the Keil 8051 tools with the Silicon Laboratories IDE. To build an absolute object file using the Silicon Laboratories IDE project manager, you must first create a project. A project consists of a set of files, IDE configuration, debug views, and a target build configuration (list of files and tool configurations used as input to the assembler, compiler, and linker when building an output object file).
  • Page 4: Example Source Code

    C8051T60x-DK 5.4.2. Building and Downloading the Program for Debugging 1. Once all source files have been added to the target build, build the project by clicking on the Build/Make → Project button in the toolbar or selecting Project Build/Make Project from the menu.
  • Page 5: Development Boards

    C8051T60x-DK 7. Development Boards The C8051T60x Development Kit includes a main board which interfaces to various daughter boards. The “C8051T600 Emulation Daughter Board” contains a C8051F300 device to be used for preliminary software development. The socketed C8051T600 daughter boards allow programming and evaluation of the actual C8051T60x family of devices.
  • Page 6 C8051T60x-DK C8051T600 EDB F300 Figure 3. C8051T600 Evaluation Daughter Board (Included in Kit) C8051T600 SOIC SKT DB PIN1 PIN14 PIN2 PIN7 PIN8 Figure 4. C8051T600 SOIC Socket Daughter Board (Included in Kit) C8051T600 QFN11 SKT DB Figure 5. C8051T600 QFN Socket Daughter Board (Available Separately)
  • Page 7 C8051T60x-DK 7.1. System Clock Sources The C8051T60x devices feature a calibrated internal oscillator which is enabled as the system clock source on reset. After reset, the internal oscillator operates at a frequency of 24.5 MHz (±2%) by default, but may be configured by software to operate at other frequencies.
  • Page 8 C8051T60x-DK 7.4. PORT I/O Connector (J8) Each of the C8051T60x’s I/O pins, as well as VPP, +3VD, GND, and /RST are routed to header J8. This header can be used to easily connect to any signal on the device. Table 2 defines the pins for header J8.
  • Page 9 C8051T60x-DK 7.7. VPP Connection (J10) The C8051T60x devices require a special 6.5 V programming voltage applied to the VPP pin during device programming. The VPP pin on these devices is shared with P0.2. During programming, the VPP voltage is automatically enabled when needed. Header J10 is provided to allow the user to disconnect the programming circuitry from the VPP/P0.2 pin to avoid interfering with the normal application operation of P0.2.
  • Page 10 C8051T60x-DK 8. Schematics Rev. 0.1...
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  • Page 16 Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per- sonal injury or death may occur.