Mode 1: 16-Bit Counter/Timer; Mode 2: 8-Bit Counter/Timer With Auto-Reload; Figure 28.1. T0 Mode 0 Block Diagram - Silicon Laboratories C8051T620 Manual

Setting TR0 does not force the timer to reset. The timer registers should be loaded with the desired initial
value before the timer is enabled.
TL1 and TH1 form the 13-bit register for Timer 1 in the same manner as described above for TL0 and TH0.
Timer 1 is configured and controlled using the relevant TCON and TMOD bits just as with Timer 0. The
input signal INT1 is used with Timer 1; the INT1 polarity is defined by bit IN1PL in register IT01CF (see
SFR Definition 17.7).
Pre-scaled Clock
SYSCLK
T0
Crossbar
IN0PL
INT0

28.1.2. Mode 1: 16-bit Counter/Timer

Mode 1 operation is the same as Mode 0, except that the counter/timer registers use all 16 bits. The coun-
ter/timers are enabled and configured in Mode 1 in the same manner as for Mode 0.

28.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload

Mode 2 configures Timer 0 and Timer 1 to operate as 8-bit counter/timers with automatic reload of the start
value. TL0 holds the count and TH0 holds the reload value. When the counter in TL0 overflows from all
ones to 0x00, the timer overflow flag TF0 in the TCON register is set and the counter in TL0 is reloaded
from TH0. If Timer 0 interrupts are enabled, an interrupt will occur when the TF0 flag is set. The reload
value in TH0 is not changed. TL0 must be initialized to the desired value before enabling the timer for the
first count to be correct. When in Mode 2, Timer 1 operates identically to Timer 0.
Both counter/timers are enabled and configured in Mode 2 in the same manner as Mode 0. Setting the
TR0 bit (TCON.4) enables the timer when either GATE0 in the TMOD register is logic 0 or when the input
signal INT0 is active as defined by bit IN0PL in register IT01CF (see Section "17.3. INT0 and INT1 External
Interrupt Sources" on page 110 for details on the external input signals INT0 and INT1).
C8051T620/1/6/7 & C8051T320/1/2/3
G
A
T0M
T
E
1
0
0
1
1
TR0
GATE0
XOR

Figure 28.1. T0 Mode 0 Block Diagram

Rev. 1.2
TMOD IT01CF
C T T G C T T I I I I I I I I
/ 1 1 A / 0 0 N N N N N N N N
T M M T T M M 1 1 1 1 0 0 0 0
1 1 0 E 0 1 0 P S S S P S S S
0 L L L L L L L L
2 1 0 2 1 0
TCLK TL0 TH0
(5 bits) (8 bits)
TF1
TR1
TF0
Interrupt
TR0
IE1
IT1
IE0
IT0
249