Comparator Multiplexers; Figure 14.4. Comparator Input Multiplexer Block Diagram - Silicon Laboratories C8051T620 Manual

C8051T620/1/6/7 & C8051T320/1/2/3

14.1. Comparator Multiplexers

C8051T620/1/6/7 & C8051T320/1/2/3 devices include an analog input multiplexer to connect Port I/O pins
to the comparator inputs. The Comparator inputs are selected in the CPTnMX registers (SFR Definition
14.5 and SFR Definition 14.6). The CMXnP2–CMXnP0 bits select the Comparator positive input; the
CMXnN2–CMXnN0 bits select the Comparator negative input.
Important Note About Comparator Inputs: The Port pins selected as comparator inputs should be con-
figured as analog inputs in their associated Port configuration register, and configured to be skipped by the
Crossbar (for details on Port configuration, see Section "22.6. Special Function Registers for Accessing
and Configuring Port I/O" on page 152).
CPT0MX
P1.0
P1.4
P2.0
P2.4
P0.0
CP0 +
CP0 -
P1.1
P1.5
P2.1
P2.5
P0.1

Figure 14.4. Comparator Input Multiplexer Block Diagram

84
VDD
+
-
GND
Rev. 1.2
CPT1MX
P1.2
P1.6
P2.2
P0.4
CP1 +
CP1 -
P1.3
P1.7
P2.3
P0.5
VDD
+
-
GND