Watchdog Timer Mode; Watchdog Timer Operation; Figure 29.10. Pca 16-Bit Pwm Mode - Silicon Laboratories C8051T620 Manual

Write to
0
PCA0CPLn
ENB
Reset
Write to
PCA0CPHn ENB
1
PCA0CPMn
P
E C C
W
C A A
M
O P P
1
M P N
6
n n n
n
1 0 0 x 0

29.4. Watchdog Timer Mode

A programmable watchdog timer (WDT) function is available through the PCA Module 4. The WDT is used
to generate a reset if the time between writes to the WDT update register (PCA0CPH4) exceed a specified
limit. The WDT can be configured and enabled/disabled as needed by software.
With the WDTE bit set in the PCA0MD register, Module 4 operates as a watchdog timer (WDT). The Mod-
ule 4 high byte is compared to the PCA counter high byte; the Module 4 low byte holds the offset to be
used when WDT updates are performed. The Watchdog Timer is enabled on reset. Writes to some
PCA registers are restricted while the Watchdog Timer is enabled. The WDT will generate a reset
shortly after code begins execution. To avoid this reset, the WDT should be explicitly disabled (and option-
ally re-configured and re-enabled if it is used in the system).

29.4.1. Watchdog Timer Operation

While the WDT is enabled:
 PCA counter is forced on.
 Writes to PCA0L and PCA0H are not allowed.
 PCA clock source bits (CPS2–CPS0) are frozen.
 PCA Idle control bit (CIDL) is frozen.
 Module 4 is forced into software timer mode.
 Writes to the Module 4 mode register (PCA0CPM4) are disabled.
While the WDT is enabled, writes to the CR bit will not change the PCA counter state; the counter will run
until the WDT is disabled. The PCA counter run control bit (CR) will read zero if the WDT is enabled but
user software has not enabled the PCA counter. If a match occurs between PCA0CPH4 and PCA0H while
the WDT is enabled, a reset will be generated. To prevent a WDT reset, the WDT may be updated with a
write of any value to PCA0CPH4. Upon a PCA0CPH4 write, PCA0H plus the offset held in PCA0CPL4 is
loaded into PCA0CPH4 (See Figure 29.11).
C8051T620/1/6/7 & C8051T320/1/2/3
P
M T E
W
A O C
PCA0CPHn
M
T G C
n
n n F
n
x
Enable
16-bit Comparator
PCA Timebase
PCA0H

Figure 29.10. PCA 16-Bit PWM Mode

Rev. 1.2
PCA0CPLn
match
SET
S Q
R Q
CLR
PCA0L
Overflow
CEXn
Crossbar Port I/O
279