Sfr Definition 29.5. Pca0L: Pca Counter/Timer Low Byte; Sfr Definition 29.6. Pca0H: Pca Counter/Timer High Byte - Silicon Laboratories C8051T620 Manual

C8051T620/1/6/7 & C8051T320/1/2/3

SFR Definition 29.5. PCA0L: PCA Counter/Timer Low Byte

Bit 7
Name
Type R/W R/W
Reset 0
SFR Address = 0xF9
Bit Name
7:0 PCA0[7:0] PCA Counter/Timer Low Byte.
The PCA0L register holds the low byte (LSB) of the 16-bit PCA Counter/Timer.
Note: When the WDTE bit is set to 1, the PCA0L register cannot be modified by software. To change the contents of
the PCA0L register, the Watchdog Timer must first be disabled.

SFR Definition 29.6. PCA0H: PCA Counter/Timer High Byte

Bit 7
Name
Type R/W R/W
Reset 0
SFR Address = 0xFA
Bit Name
7:0 PCA0[15:8] PCA Counter/Timer High Byte.
The PCA0H register holds the high byte (MSB) of the 16-bit PCA Counter/Timer.
Reads of this register will read the contents of a "snapshot" register, whose contents
are updated only when the contents of PCA0L are read (see Section 29.1).
Note: When the WDTE bit is set to 1, the PCA0H register cannot be modified by software. To change the contents of
the PCA0H register, the Watchdog Timer must first be disabled.
286
6 5 4
R/W R/W
0 0 0
6 5 4
R/W R/W
0 0 0
Rev. 1.2
3 2
PCA0[7:0]
R/W R/W
0 0
Function
3 2
PCA0[15:8]
R/W R/W
0 0
Function
1 0
R/W R/W
0 0
1 0
R/W R/W
0 0